Chapter 3 Digital Design and Computer Architecture , 2 nd Edition - PowerPoint PPT Presentation

FSM Encoded State Transition Table Current State Inputs Next State S 1 S 0 T A T B S' 1 S' 0 State Encoding 0 0 0 X 0 1 S0 00 0 0 1 X 0 0 S1 01 0 1 X X 1 0 1 0 X 0 1 1 S2 10 1 0 X 1 1 0 S3 11 1 1 X X 0 0 S' 1 = S 1 Å S 0 S' 0 = S 1 S 0 T A + S 1 S 0 T B Chapter 3 <39>

FSM Output Table Current State Outputs Output Encoding S 1 S 0 L A 1 L A 0 L B 1 L B 0 green 00 0 0 0 1 yellow 01 1 0 red 10 1 1 Chapter 3 <40>

FSM Output Table Current State Outputs Output Encoding S 1 S 0 L A 1 L A 0 L B 1 L B 0 green 00 0 0 0 0 1 0 0 1 0 1 1 0 yellow 01 1 0 1 0 0 0 red 10 1 1 1 0 0 1 L A 1 = S 1 L A 0 = S 1 S 0 L B 1 = S 1 L B 0 = S 1 S 0 Chapter 3 <41>

FSM Schematic: State Register CLK S' 1 S 1 S' 0 S 0 r Reset state register Chapter 3 <42>

FSM Schematic: Next State Logic CLK S' 1 S 1 T A S' 0 S 0 r T B Reset S 1 S 0 inputs next state logic state register Chapter 3 <43>

FSM Schematic: Output Logic CLK L A1 S' 1 S 1 L A0 T A S' 0 S 0 L B1 r T B Reset S 1 S 0 L B0 inputs next state logic state register output logic outputs Chapter 3 <44>

FSM Timing Diagram Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 CLK Reset T A T B S' 1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01) S 1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) L A1:0 ?? Green (00) Yellow (01) Red (10) Green (00) L B1:0 ?? Red (10) Green (00) Yellow (01) Red (10) t (sec) 0 5 10 15 20 25 30 35 40 45 T A Reset T A S0 S1 L A : green L A : yellow L B : red L B : red S3 S2 L A : red L A : red L B : yellow L B : green T B T B Chapter 3 <45>

FSM State Encoding • Binary encoding: – i.e., for four states, 00, 01, 10, 11 • One-hot encoding – One state bit per state – Only one state bit HIGH at once – i.e., for 4 states, 0001, 0010, 0100, 1000 – Requires more flip-flops – Often next state and output logic is simpler Chapter 3 <46>

Moore vs. Mealy FSM • Alyssa P. Hacker has a snail that crawls down a paper tape with 1’s and 0’s on it. The snail smiles whenever the last two digits it has crawled over are 01. Design Moore and Mealy FSMs of the snail’s brain. Chapter 3 <47>

State Transition Diagrams Moore FSM Reset 0 1 S0 S1 S2 0 0 1 1 0 0 1 Mealy FSM Reset 0/0 S0 S1 1/0 0/0 1/1 Mealy FSM: arcs indicate input/output Chapter 3 <48>

Moore FSM State Transition Table Current State Encoding Inputs Next State State S 1 S 0 A S' 1 S' 0 S0 00 0 0 0 S1 01 0 0 1 0 1 0 S2 10 0 1 1 1 0 0 1 0 1 Chapter 3 <49>

Moore FSM State Transition Table Current State Encoding Inputs Next State State S 1 S 0 A S' 1 S' 0 S0 00 0 0 0 0 1 S1 01 0 0 1 0 0 0 1 0 0 1 S2 10 0 1 1 1 0 1 0 0 0 1 1 0 1 0 0 S 1 ’ = S 0 A S 0 ’ = A Chapter 3 <50>

Moore FSM Output Table Current State Output S 1 S 0 Y 0 0 0 1 1 0 Chapter 3 <51>

Moore FSM Output Table Current State Output S 1 S 0 Y 0 0 0 0 1 0 1 0 1 Y = S 1 Chapter 3 <52>

Mealy FSM State Transition & Output Table Current Next State Input State Output S 0 A S' 0 Y State Encoding 0 0 S0 00 0 1 1 0 S1 01 1 1 Chapter 3 <53>

Mealy FSM State Transition & Output Table Current Next State Input State Output S 0 A S' 0 Y State Encoding 0 0 1 0 S0 00 0 1 0 0 1 0 1 0 S1 01 1 1 0 1 Chapter 3 <54>

Moore FSM Schematic A CLK S' 1 S 1 Y S' 0 S 0 r Reset Chapter 3 <55>

Mealy FSM Schematic A CLK S' 0 S 0 Y r Reset Chapter 3 <56>

Moore & Mealy Timing Diagram Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Cycle 11 CLK Reset A 0 1 0 1 1 0 1 1 1 Moore Machine S ?? S0 S1 S2 S1 S2 S0 S1 S2 S0 Y Mealy Machine S ?? S0 S1 S0 S1 S0 S1 S0 Y Chapter 3 <57>

Factoring State Machines • Break complex FSMs into smaller interacting FSMs • Example: Modify traffic light controller to have Parade Mode. – Two more inputs: P , R – When P = 1 , enter Parade Mode & Bravado Blvd light stays green – When R = 1 , leave Parade Mode Chapter 3 <58>

Parade FSM Unfactored FSM P R L A Controller T A FSM L B T B Factored FSM P Mode FSM R M T A L A Lights FSM T B L B Controller FSM Chapter 3 <59>

Unfactored FSM P T A P T A R T A R T A Reset P T A S0 S1 R T A R T A S4 S5 L A : green L A : yellow P L A : green L A : yellow L B : red L B : red L B : red L B : red R P P T A P R P R P T B R S3 S2 S7 S6 L A : red L A : red L A : red L A : red L B : yellow L B : green P T B L B : yellow L B : green R P R T B R T B Chapter 3 <60>

Factored FSM T A Reset T A S0 S1 L A : green L A : yellow L B : red L B : red P Reset P S3 S2 S0 S1 L A : red L A : red M: 0 M: 1 L B : yellow L B : green R MT B M + T B R Lights FSM Mode FSM Chapter 3 <61>

FSM Design Procedure 1. Identify inputs and outputs 2. Sketch state transition diagram 3. Write state transition table 4. Select state encodings 5. For Moore machine: 1. Rewrite state transition table with state encodings 2. Write output table 6. For a Mealy machine: 1. Rewrite combined state transition and output table with state encodings 7. Write Boolean equations for next state and output logic 8. Sketch the circuit schematic Chapter 3 <62>

Timing • Flip-flop samples D at clock edge • D must be stable when sampled • Similar to a photograph, D must be stable around clock edge • If not, metastability can occur Chapter 3 <63>

Input Timing Constraints • Setup time: t setup = time before clock edge data must be stable (i.e. not changing) • Hold time: t hold = time after clock edge data must be stable • Aperture time: t a = time around clock edge data must be stable ( t a = t setup + t hold ) CLK D t setup t hold t a Chapter 3 <64>

Output Timing Constraints • Propagation delay: t pcq = time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing) • Contamination delay: t ccq = time after clock edge that Q might be unstable (i.e., start changing) CLK Q t ccq t pcq Chapter 3 <65>

Dynamic Discipline • Synchronous sequential circuit inputs must be stable during aperture (setup and hold) time around clock edge • Specifically, inputs must be stable – at least t setup before the clock edge – at least until t hold after the clock edge Chapter 3 <66>

Dynamic Discipline • The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements CLK CLK Q1 D2 C L R1 R2 (a) T c CLK Q1 D2 (b) Chapter 3 <67>

Setup Time Constraint • Depends on the maximum delay from register R1 through combinational logic to R2 • The input to register R2 must be stable at least t setup before clock edge CLK CLK Q1 D2 C T c ≥ L R1 R2 T c CLK Q1 D2 t pcq t pd t setup Chapter 3 <68>

Setup Time Constraint • Depends on the maximum delay from register R1 through combinational logic to R2 • The input to register R2 must be stable at least t setup before clock edge CLK CLK Q1 D2 C T c ≥ t pcq + t pd + t setup L R1 R2 t pd ≤ T c CLK Q1 D2 t pcq t pd t setup Chapter 3 <69>

Setup Time Constraint • Depends on the maximum delay from register R1 through combinational logic to R2 • The input to register R2 must be stable at least t setup before clock edge CLK CLK Q1 D2 C T c ≥ t pcq + t pd + t setup L R1 R2 t pd ≤ T c – ( t pcq + t setup ) T c CLK Q1 ( t pcq + t setup ) : sequencing overhead D2 t pcq t pd t setup Chapter 3 <70>

Hold Time Constraint • Depends on the minimum delay from register R1 through the combinational logic to R2 • The input to register R2 must be stable for at least t hold after the clock edge CLK CLK Q1 D2 C L t hold < R1 R2 CLK Q1 D2 t ccq t cd t hold Chapter 3 <71>

Hold Time Constraint • Depends on the minimum delay from register R1 through the combinational logic to R2 • The input to register R2 must be stable for at least t hold after the clock edge CLK CLK Q1 D2 C L t hold < t ccq + t cd R1 R2 t cd > CLK Q1 D2 t ccq t cd t hold Chapter 3 <72>

Hold Time Constraint • Depends on the minimum delay from register R1 through the combinational logic to R2 • The input to register R2 must be stable for at least t hold after the clock edge CLK CLK Q1 D2 C L t hold < t ccq + t cd R1 R2 t cd > t hold - t ccq CLK Q1 D2 t ccq t cd t hold Chapter 3 <73>

Timing Analysis Timing Characteristics CLK CLK A t ccq = 30 ps t pcq = 50 ps B t setup = 60 ps X' X C t hold = 70 ps Y' Y D per gate t pd = 35 ps t cd = 25 ps t pd = t cd = Setup time constraint: Hold time constraint: T c ≥ t ccq + t cd > t hold ? f c = Chapter 3 <74>

Timing Analysis Timing Characteristics CLK CLK A t ccq = 30 ps t pcq = 50 ps B t setup = 60 ps X' X C t hold = 70 ps Y' Y D per gate t pd = 35 ps t cd = 25 ps t pd = 3 x 35 ps = 105 ps t cd = 25 ps Setup time constraint: Hold time constraint: T c ≥ (50 + 105 + 60) ps = 215 ps t ccq + t cd > t hold ? f c = 1/ T c = 4.65 GHz (30 + 25) ps > 70 ps ? No! Chapter 3 <75>

Timing Analysis Timing Characteristics Add buffers to the short paths: CLK CLK t ccq = 30 ps A t pcq = 50 ps t setup = 60 ps B t hold = 70 ps X' X C Y' Y D per gate t pd = 35 ps t cd = 25 ps t pd = t cd = Setup time constraint: Hold time constraint: T c ≥ t ccq + t cd > t hold ? f c = Chapter 3 <76>

Timing Analysis Timing Characteristics Add buffers to the short paths: CLK CLK t ccq = 30 ps A t pcq = 50 ps t setup = 60 ps B t hold = 70 ps X' X C Y' Y D per gate t pd = 35 ps t cd = 25 ps t pd = 3 x 35 ps = 105 ps t cd = 2 x 25 ps = 50 ps Setup time constraint: Hold time constraint: T c ≥ (50 + 105 + 60) ps = 215 ps t ccq + t cd > t hold ? f c = 1/ T c = 4.65 GHz (30 + 50) ps > 70 ps ? Yes! Chapter 3 <77>

Clock Skew • The clock doesn’t arrive at all registers at same time • Skew: difference between two clock edges • Perform worst case analysis to guarantee dynamic discipline is not violated for any register – many registers in a system! delay CLK CLK1 CLK2 Q1 D2 C L R1 R2 t skew CLK1 CLK2 CLK Chapter 3 <78>

Setup Time Constraint with Skew • In the worst case, CLK2 is earlier than CLK1 CLK1 CLK2 Q1 D2 C L R1 R2 T c CLK1 T c ≥ CLK2 Q1 D2 t pcq t pd t setup t skew Chapter 3 <79>

Setup Time Constraint with Skew • In the worst case, CLK2 is earlier than CLK1 CLK1 CLK2 Q1 D2 C L R1 R2 T c CLK1 T c ≥ t pcq + t pd + t setup + t skew CLK2 t pd ≤ Q1 D2 t pcq t pd t setup t skew Chapter 3 <80>

Setup Time Constraint with Skew • In the worst case, CLK2 is earlier than CLK1 CLK1 CLK2 Q1 D2 C L R1 R2 T c CLK1 T c ≥ t pcq + t pd + t setup + t skew CLK2 t pd ≤ T c – ( t pcq + t setup + t skew ) Q1 D2 t pcq t pd t setup t skew Chapter 3 <81>

Hold Time Constraint with Skew • In the worst case, CLK2 is later than CLK1 CLK1 CLK2 Q1 D2 C L R1 R2 CLK1 t ccq + t cd > CLK2 Q1 D2 t ccq t cd t skew t hold Chapter 3 <82>

Hold Time Constraint with Skew • In the worst case, CLK2 is later than CLK1 CLK1 CLK2 Q1 D2 C L R1 R2 CLK1 t ccq + t cd > t hold + t skew CLK2 t cd > Q1 D2 t ccq t cd t skew t hold Chapter 3 <83>

Hold Time Constraint with Skew • In the worst case, CLK2 is later than CLK1 CLK1 CLK2 Q1 D2 C L R1 R2 CLK1 t ccq + t cd > t hold + t skew CLK2 t cd > t hold + t skew – t ccq Q1 D2 t ccq t cd t skew t hold Chapter 3 <84>

Violating the Dynamic Discipline • Asynchronous (for example, user) t setup t hold inputs might violate the dynamic discipline CLK CLK button t aperture D D Q Case I Q D Case II Q D Case III ??? Q Chapter 3 <85>

Metastability • Bistable devices: two stable states, and a metastable state between them • Flip-flop: two stable states (1 and 0) and one metastable state • If flip-flop lands in metastable state, could stay there for an undetermined amount of time metastable stable stable Chapter 3 <86>

Flip-Flop Internals • Flip-flop has feedback : if Q is somewhere between 1 and 0, cross-coupled gates drive output to either rail (1 or 0) R N1 Q N2 Q S • Metastable signal: if it hasn’t resolved to 1 or 0 • If flip-flop input changes at random time, probability that output Q is metastable after waiting some time, t : P( t res > t ) = ( T 0 / T c ) e - t / τ t res : time to resolve to 1 or 0 T 0 , τ : properties of the circuit Chapter 3 <87>

Metastability • Intuitively: T 0 / T c : probability input changes at a bad time (during aperture) P( t res > t ) = ( T 0 / T c ) e - t / τ τ : time constant for how fast flip-flop moves away from metastability P( t res > t ) = ( T 0 / T c ) e - t / τ • In short, if flip-flop samples metastable input, if you wait long enough ( t ), the output will have resolved to 1 or 0 with high probability. Chapter 3 <88>

Synchronizers • Asynchronous inputs are inevitable (user interfaces, systems with different clocks interacting, etc.) • Synchronizer goal: make the probability of failure (the output Q still being metastable) low • Synchronizer cannot make the probability of failure 0 CLK SYNC D Q Chapter 3 <89>

Synchronizer Internals • Synchronizer: built with two back-to-back flip-flops • Suppose D is transitioning when sampled by F1 • Internal signal D2 has ( T c - t setup ) time to resolve to 1 or 0 CLK CLK D2 D Q F1 F2 T c CLK D2 metastable Q t res t setup t pcq Chapter 3 <90>

Synchronizer Probability of Failure For each sample, probability of failure is: P(failure) = ( T 0 / T c ) e - (T c - t setup ) / τ CLK CLK D2 D Q F1 F2 T c CLK D2 metastable Q t res t setup t pcq Chapter 3 <91>

Synchronizer Mean Time Between Failures • If asynchronous input changes once per second, probability of failure per second is P (failure). • If input changes N times per second, probability of failure per second is: P (failure)/second = ( NT 0 / T c ) e - (T c - t setup ) / τ • Synchronizer fails, on average, 1/[ P (failure)/second] • Called mean time between failures , MTBF: MTBF = 1/[ P (failure)/second] = ( T c / NT 0 ) e (T c - t setup ) / τ Chapter 3 <92>

Example Synchronizer CLK CLK D2 D Q F1 F2 • Suppose: T c = 1/500 MHz = 2 ns τ = 200 ps T 0 = 150 ps t setup = 100 ps N = 10 events per second • What is the probability of failure? MTBF? Chapter 3 <93>

Example Synchronizer CLK CLK D2 D Q F1 F2 • Suppose: T c = 1/500 MHz = 2 ns τ = 200 ps T 0 = 150 ps t setup = 100 ps N = 10 events per second • What is the probability of failure? MTBF? P (failure) = (150 ps/2 ns) e - ( 1.9 ns ) /200 ps = 5.6 × 10 -6 P (failure)/second = 10 × (5.6 × 10 -6 ) = 5.6 × 10 -5 / second MTBF = 1/[P(failure)/second] ≈ 5 hours Chapter 3 <94>

Parallelism • Two types of parallelism: – Spatial parallelism • duplicate hardware performs multiple tasks at once – Temporal parallelism • task is broken into multiple stages • also called pipelining • for example, an assembly line Chapter 3 <95>

Parallelism Definitions • Token: Group of inputs processed to produce group of outputs • Latency: Time for one token to pass from start to end • Throughput: Number of tokens produced per unit time Parallelism increases throughput Chapter 3 <96>

Parallelism Example • Ben Bitdiddle bakes cookies to celebrate traffic light controller installation • 5 minutes to roll cookies • 15 minutes to bake • What is the latency and throughput without parallelism? Chapter 3 <97>

Parallelism Example • Ben Bitdiddle bakes cookies to celebrate traffic light controller installation • 5 minutes to roll cookies • 15 minutes to bake • What is the latency and throughput without parallelism? Latency = 5 + 15 = 20 minutes = 1/3 hour Throughput = 1 tray/ 1/3 hour = 3 trays/hour Chapter 3 <98>

Parallelism Example • What is the latency and throughput if Ben uses parallelism? – Spatial parallelism: Ben asks Allysa P. Hacker to help, using her own oven – Temporal parallelism: • two stages: rolling and baking • He uses two trays • While first batch is baking, he rolls the second batch, etc. Chapter 3 <99>

Spatial Parallelism Latency: time to first tray 0 5 10 15 20 25 30 35 40 45 50 Time Tray 1 Ben 1 Ben 1 Roll Parallelism Tray 2 Alyssa 1 Alyssa 1 Spatial Bake Tray 3 Ben 2 Ben 2 Legend Tray 4 Alyssa 2 Alyssa 2 Latency = ? Throughput = ? Chapter 3 <100>