Operating Systems: Chapter 1 Internals and Computer System Design Overview Principles Eighth Edition By William Stallings
Operating System Operating System � Exploits the hardware resources of one or more processors � Provides a set of services to system users � Manages secondary memory and I/O devices
Basic Elements Basic Elements
Processor Processor
Main Memory Main Memory � Volatile � Contents of the memory is lost when the computer is shut down � Referred to as real memory or primary memory
I/O Modules I/O Modules
System Bus System Bus � Provides for communication among processors, main memory, and I/O modules
CPU Main Memory 0 System 1 2 Bus PC MAR Instruction Instruction Instruction IR MBR I/O AR Data Execution Data unit I/O BR Data Data I/O Module n - 2 n - 1 PC = Program counter IR = Instruction register Buffers MAR = Memory address register MBR = Memory buffer register I/O AR = Input/output address register I/O BR = Input/output buffer register Figure 1.1 Computer Components: Top-Level View
Microprocessor Microprocessor � Invention that brought about desktop and handheld computing � Processor on a single chip � Fastest general purpose processor � Multiprocessors � Each chip (socket) contains multiple processors (cores)
Graphical Processing Graphical Processing Units (GPU’ ’s) s) Units (GPU � Provide efficient computation on arrays of data using Single-Instruction Multiple Data (SIMD) techniques � Used for general numerical processing � Physics simulations for games � Computations on large spreadsheets
Digital Signal Processors Digital Signal Processors (DSPs) (DSPs) � Deal with streaming signals such as audio or video � Used to be embedded in devices like modems � Encoding/decoding speech and video (codecs) � Support for encryption and security
System on a Chip System on a Chip (SoC) (SoC) � To satisfy the requirements of handheld devices, the microprocessor is giving way to the SoC � Components such as DSPs, GPUs, codecs and main memory, in addition to the CPUs and caches, are on the same chip
Instruction Execution Instruction Execution � A program consists of a set of instructions stored in memory Two steps
Fetch Stage Execute Stage Fetch Next Execute HALT START Instruction Instruction Figure 1.2 Basic Instruction Cycle
� The processor fetches the instruction from memory � Program counter (PC) holds address of the instruction to be fetched next � PC is incremented after each fetch
Instruction Register (IR) Instruction Register (IR) � Processor interprets the Fetched instruction is instruction and loaded into Instruction performs required Register (IR) action: � Processor-memory � Processor-I/O � Data processing � Control
Fetch Stage Execute Stage Memory CPU Registers Memory CPU Registers 300 1 9 4 0 3 0 0 PC 300 1 9 4 0 3 0 1 PC 301 5 9 4 1 AC 301 5 9 4 1 AC 0 0 0 3 302 2 9 4 1 IR 302 2 9 4 1 IR 1 9 4 0 1 9 4 0 • • • • 940 0 0 0 3 940 0 0 0 3 941 0 0 0 2 941 0 0 0 2 Step 1 Step 2 Memory CPU Registers Memory CPU Registers 300 1 9 4 0 3 0 1 PC 300 1 9 4 0 3 0 2 PC 301 5 9 4 1 AC 301 5 9 4 1 AC 0 0 0 3 1 0 0 0 5 302 2 9 4 1 IR 302 2 9 4 1 IR 5 9 4 1 5 9 4 1 • • • • 940 0 0 0 3 940 0 0 0 3 3 + 2 = 5 941 0 0 0 2 941 0 0 0 2 Step 3 Step 4 Memory CPU Registers Memory CPU Registers 300 1 9 4 0 3 0 2 PC 300 1 9 4 0 3 0 3 PC 301 5 9 4 1 AC 301 5 9 4 1 AC 0 0 0 5 0 0 0 5 302 2 9 4 1 2 9 4 1 IR 302 2 9 4 1 2 9 4 1 IR • • • • 940 0 0 0 3 940 0 0 0 3 941 0 0 0 2 941 0 0 0 5 Step 5 Step 6 Figure 1.4 Example of Program Execution (contents of memory and registers in hexadecimal)
Interrupts Interrupts � Interrupt the normal sequencing of the processor � Provided to improve processor utilization � most I/O devices are slower than the processor � processor must pause to wait for device � wasteful use of the processor
Table 1.1 Classes of Interrupts Program Generated by some condition that occurs as a result of an instruction execution, such as arithmetic overflow, division by zero, attempt to execute an illegal machine instruction, and reference outside a user's allowed memory space. Timer Generated by a timer within the processor. This allows the operating system to perform certain functions on a regular basis. I/O Generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error conditions. Hardware Generated by a failure, such as power failure or memory failure parity error.
User I/O Program Program 4 1 I/O Command WRITE Figure 1.5a 5 END 2 Flow of Control WRITE Without Interrupts 3 WRITE (a) No interrupts
User I/O Program Program 4 1 I/O Command WRITE 2a Figure 1.5b Interrupt 2b Handler 5 WRITE Short I/O Wait END 3a 3b WRITE (b) Interrupts; short I/O wait
User I/O Program Program 4 1 I/O Command WRITE Figure 1.5c 2 Interrupt Handler 5 WRITE Long I/O Wait END 3 WRITE (c) Interrupts; long I/O wait
User Program Interrupt Handler 1 2 i Interrupt occurs here i + 1 M Figure 1.6 Transfer of Control via Interrupts
Fetch Stage Execute Stage Interrupt Stage Interrupts Disabled Check for interrupt; Fetch next Execute START instruction instruction initiate interrupt Interrupts handler Enabled HALT Figure 1.7 Instruction Cycle with Interrupts
Time 1 1 4 4 I/O operation I/O operation; 2a concurrent with processor waits processor executing 5 5 2b 2 4 I/O operation 4 3a concurrent with processor executing I/O operation; 5 processor waits 5 3b (b) With interrupts 3 (a) Without interrupts Figure 1.8 Program Timing: Short I/O Wait
Time 1 1 4 4 I/O operation; 2 I/O operation processor waits concurrent with processor executing; then processor waits 5 5 2 4 4 3 I/O operation concurrent with I/O operation; processor executing; processor waits then processor waits 5 5 3 (b) With interrupts (a) Without interrupts Figure 1.9 Program Timing: Long I/O Wait
Hardware Software Device controller or other system hardware issues an interrupt Save remainder of process state information Processor finishes execution of current instruction Process interrupt Processor signals acknowledgment of interrupt Restore process state information Processor pushes PSW and PC onto control stack Restore old PSW and PC Processor loads new PC value based on interrupt Figure 1.10 Simple Interrupt Processing
T – M T – M N + 1 Y Control Control Stack Stack T T N + 1 Y + L + 1 Program Program Counter Counter Start Start Y Y General General Interrupt Interrupt Registers Registers Service Service Routine Routine Y + L Y + L Return Return T T – M Stack Stack Pointer Pointer Processor Processor T – M T N N User's User's N + 1 N + 1 Program Program Main Main Memory Memory (a) Interrupt occurs after instruction (b) Return from interrupt at location N Figure 1.11 Changes in Memory and Registers for an Interrupt
Multiple Interrupts Multiple Interrupts
Interrupt Handler X User Program Interrupt Handler Y (a) Sequential interrupt processing Interrupt Handler X User Program Interrupt Handler Y (b) Nested interrupt processing Figure 1.12 Transfer of Control with Multiple Interrupts
Printer Communication User Program interrupt service routine interrupt service routine t = 0 t = 1 5 t = 10 t = 2 5 Disk t = 25 t = 40 interrupt service routine t = 3 5 Figure 1.13 Example Time Sequence of Multiple Interrupts
Memory Hierarchy Memory Hierarchy � Major constraints in memory � amount � speed � expense � Memory must be able to keep up with the processor � Cost of memory must be reasonable in relationship to the other components
Memory Relationships Memory Relationships
The Memory Hierarchy The Memory Hierarchy � Going down the Reg- isters I Cache n b hierarchy: o M a r e d m Main o Memory r y Magnetic Disk O u t CD-ROM b o � decreasing cost per bit S a t o r CD-RW d r a DVD-RW g e DVD-RAM Blu-Ray � increasing capacity Magnetic Tape � increasing access time O f f - l S i n t e o r a g e � decreasing frequency of access to the memory by the processor Figure 1.14 The Memory Hierarchy
T 1 + T 2 T 2 Average access time T 1 0 1 Fraction of accesses involving only Level 1 (Hit ratio) Figure 1.15 Performance of a Simple Two-Level Memory
� Memory references by the processor tend to cluster � Data is organized so that the percentage of accesses to each successively lower level is substantially less than that of the level above � Can be applied across more than two levels of memory
� Invisible to the OS � Interacts with other memory management hardware � Processor must access memory at least once per instruction cycle � Processor execution is limited by memory cycle time � Exploit the principle of locality with a small, fast memory
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