Cache Digests for HTTP/2 Kazuho Oku Cache Digest (IETF 100) Pull - PowerPoint PPT Presentation

Jan 03, 2023 •221 likes •289 views

Cache Digests for HTTP/2 Kazuho Oku Cache Digest (IETF 100) Pull Request #413 proposes: SENDING_CACHE_DIGEST SETTINGS Parameter switch to Cuckoo hashing thanks to Yoav Weiss for the proposal Cache Digest (IETF 100)

Cache Digests for HTTP/2 Kazuho Oku Cache Digest (IETF 100)
Pull Request #413 • proposes: – SENDING_CACHE_DIGEST SETTINGS Parameter – switch to Cuckoo hashing – thanks to Yoav Weiss for the proposal Cache Digest (IETF 100)
SENDING_CACHE_DIGEST • a SETTINGS parameter sent by client – “I’m going to send CACHE_DIGEST, so the server should decide what to push after seeing the digest” • discussion: – CACHE_DIGEST frame has “origin” field. Do we need to associate the flag to each origin, or is SETTINGS parameter fine? – do we need a way to retract the announcement? • i.e. “I said I am going to send CACHE_DIGEST, but I cannot” Cache Digest (IETF 100)
Switch to Cuckoo Hashing • client-side: – no need to iterate through the browser cache when generating the CACHE_DIGEST frame – the hash becomes a persistent structure in the browser cache • allowing O(1) insertion and removal of URLs • O(N) when resizing happens – resizing requires additional data to be associated to the entries of the hash • server-side: – no need to decode the frame before lookup • digest becomes slightly(?) larger Cache Digest (IETF 100)
Cuckoo Hashing – no distinction bet. fresh vs. stale • what should we include in the digest? a) hash(URL): • meaningless for stale-cached responses • waste of bandwidth if the majority of cached responses are stale b) hash(URL+etag): • server needs to know the etag of the resource it might push in order to determine if it should push • client needs to respect (i.e. save) the pushed response even if it already has a freshly-cached object with the same URL • pull request proposes b Cache Digest (IETF 100)
Cuckoo Hashing – the options • a) replace Golomb Coded Sets with Cuckoo Hashing? • b) define both algorithms? – might not be an option due to the stale vs. fresh distinction • c) stick to using Golomb Coded Sets – can be generated by browser from Cuckoo Hash with additional data Cache Digest (IETF 100)

Recommend

Web Cache Consistency Web Cache Consistency Web Cache Consistency Web Cache Consistency

Web Cache Consistency Web Cache Consistency Web Cache Consistency Web Cache Consistency Requirements of performance, availability, and disconnected operation require us to relax the goal of semantic transparency. - HTTP 1.1 specification

598 views • 13 slides

1 HTTP 1.1 Expiration and Validation in HTTP 1.1 HTTP 1.1 Expiration and Validation in HTTP 1.1

Web Cache Consistency Web Cache Consistency Requirements of performance, availability, and disconnected operation require us to relax the goal of semantic transparency. - HTTP 1.1 specification Web Cache Consistency Web Cache Consistency

280 views • 3 slides

1 Classifying cache misses Cache Organization Classifying misses by causes (3Cs) Cache size,

Cache Performance Metrics Cache miss rate: number of cache misses divided by number of accesses Lecture 14: Hardware Approaches for Cache Optimizations Cache hit time: the time between sending address and data returning from cache Cache

608 views • 4 slides

L09: Cache Name: ID: Question: Direct Mapping Cache Hit Rate Consider a 4-block empty Cache,

L09: Cache Name: ID: Question: Direct Mapping Cache Hit Rate Consider a 4-block empty Cache, and all blocks initially marked as not valid , Given the main memory word addresses 0 1 2 3 4 3 4 15, calculate Cache hit rate. Cache Index

654 views • 9 slides

What Is Memory Hierarchy A typical memory hierarchy today: Lecture 13: Cache Basics and Cache

What Is Memory Hierarchy A typical memory hierarchy today: Lecture 13: Cache Basics and Cache Performance Proc/Regs L1-Cache Bigger Faster L2-Cache Memory hierarchy concept, cache L3-Cache (optional) design fundamentals, set-associative

303 views • 4 slides

DNS Session 2: DNS cache operation and DNS debugging These materials are licensed under the

DNS Session 2: DNS cache operation and DNS debugging These materials are licensed under the Creative Commons Attribution-Noncommercial 3.0 Unported license (http://creativecommons.org/licenses/by-nc/3.0/) DNS Cache Operation How caching NS works

700 views • 45 slides

Complex Tryptic Digests Andrew Alpert PolyLC Inc. Columbia, MD U.S.A. HILIC versus RP: Inverse

Israel lectures 4/10-5/10/2010 ERLIC and Proteomics: Simultaneous Isolation of Phospho- and Glycopeptides and Superior Fractionation of Complex Tryptic Digests Andrew Alpert PolyLC Inc. Columbia, MD U.S.A. HILIC versus RP: Inverse

641 views • 53 slides

Cache Performance Associativity Replacement Samira Khan Cache Performance March 28,

3/28/17 Agenda Review from last lecture Cache access Cache Performance Associativity Replacement Samira Khan Cache Performance March 28, 2017 Direct-Mapped Cache: Placement and Access Cache Abstraction and Metrics 00 | 000

518 views • 16 slides

Plan Hierarchical memories and their impact on our programs 1 Cache Memories, Cache Complexity

Plan Hierarchical memories and their impact on our programs 1 Cache Memories, Cache Complexity Cache Analysis in Practice 2 Marc Moreno Maza The Ideal-Cache Model 3 University of Western Ontario, London, Ontario (Canada) Cache Complexity

632 views • 25 slides

Generations of Cache 1980: no cache in proc; 1989 first Intel proc with a cache on chip.

Generations of Cache 1980: no cache in proc; 1989 first Intel proc with a cache on chip. 1995 2-level cache on chip Instructions Per Cycle Lost to Memory 1st Alpha 340 ns/5.0 ns = 68 clks x 2 or 136 2nd Alpha 266 ns/3.3 ns

588 views • 46 slides

Cache-timing attacks http://cr.yp.to/papers.html #cachetiming , 2005: D. J. Bernstein This

Cache-timing attacks http://cr.yp.to/papers.html #cachetiming , 2005: D. J. Bernstein This paper reports successful Thanks to: extraction of a complete AES key University of Illinois at Chicago from a network server NSF CCR9983950 on

1.28k views • 91 slides

Caches Electronic Computers M Caches 1 Cache LOCALITY PRINCIPLE (SPATIAL AND TEMPORAL)

Caches Electronic Computers M Caches 1 Cache LOCALITY PRINCIPLE (SPATIAL AND TEMPORAL) WORKING SET CPU Cache Registers Cache I lev. Cache II lev. Cache III lev. Memory Disk Tape The cache is a memory with an access time some

572 views • 55 slides

1 Locate set Cache Read Example: Direct Mapped Cache (E = 1) Check if any line in set

Today Cache memory organization and operation Performance impact of caches Cache Memories The memory mountain Rearranging loops to improve spatial locality Using blocking to improve temporal locality CSci 2021: Machine

102 views • 8 slides

CSE378 - Cache Performance metrics for caches Parameters for cache design Basic performance

CSE378 - Cache Performance metrics for caches Parameters for cache design Basic performance metric: hit ratio h Goal: Have h as high as possible without paying too much for T cache h = Number of memory references that hit in the cache /

427 views • 6 slides

Memory Hierarchy: Cache Memory hierarchy Cache basics Locality Cache organization Cache-aware

Memory Hierarchy: Cache Memory hierarchy Cache basics Locality Cache organization Cache-aware programming How does execution time grow with SIZE? int[] array = new int[SIZE]; fillArrayRandomly(array); int s = 0; for (int i = 0; i <

848 views • 48 slides

Direct Map Cache and Set Associative Cache (Revision) Lecture 14 CDA 3103 07-07-2014 Example 1

Direct Map Cache and Set Associative Cache (Revision) Lecture 14 CDA 3103 07-07-2014 Example 1 A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the

357 views • 19 slides

Cache Creek Placer Area Fee Proposal History of Placer Mining at Cache Creek Prospecting in

Cache Creek Placer Area Fee Proposal History of Placer Mining at Cache Creek Prospecting in Colorado began in 1858 1859, First discovery of gold in Cache Creek Park 1860, Campbell and Shoewalter excavated their first pits in Cache

298 views • 13 slides

Cache Memory Chapter 17 S. Dandamudi Outline Introduction Types of cache misses

Cache Memory Chapter 17 S. Dandamudi Outline Introduction Types of cache misses How cache memory works Types of caches Why cache memory works Example implementations Pentium Cache design basics PowerPC

802 views • 56 slides

Cache Memory Chapter 17 S. Dandamudi Outline Introduction Types of cache misses

Cache Memory Chapter 17 S. Dandamudi Outline Introduction Types of cache misses How cache memory works Types of caches Why cache memory works Example implementations Cache design basics Pentium PowerPC

813 views • 28 slides

Cache Memories, Cache Complexity Marc Moreno Maza University of Western Ontario, London, Ontario

Cache Memories, Cache Complexity Marc Moreno Maza University of Western Ontario, London, Ontario (Canada) CS3101 and CS4402-9635 Plan Hierarchical memories and their impact on our programs Cache Analysis in Practice The Ideal-Cache Model

1.18k views • 100 slides

General Cache Mechanics CPU Block: unit of data in cache and memory. (a.k.a. line) Memory

General Cache Mechanics CPU Block: unit of data in cache and memory. (a.k.a. line) Memory Hierarchy: Cache Smaller, faster, more expensive. Cache 8 9 14 3 Stores subset of memory blocks . (lines) Data is moved in block units Memory

467 views • 8 slides

1 Trace Cache Summary of Reducing Cache Hit Time Trace: a dynamic sequence of Small and simple

Improving Cache Performance 1. Reducing miss rates 3. Reducing miss penalty or miss rates via parallelism Larger block size Lecture 18: Reducing Cache Hit Non-blocking caches larger cache size Time and Main Memory Design

285 views • 3 slides

Cache Performance Samira Khan March 28, 2017 Agenda Review from last lecture Cache

Cache Performance Samira Khan March 28, 2017 Agenda Review from last lecture Cache access Associativity Replacement Cache Performance Cache Abstraction and Metrics Address Tag Store Data Store (stores (is the address in

904 views • 61 slides

Cache Coherency and Memory Consistency Why On-Chip Cache Coherence is here to stay - Motivation:

Cache Coherency and Memory Consistency Why On-Chip Cache Coherence is here to stay - Motivation: There is skepticism about the scalability of cache coherence: Some argue: Availability of other paradigms such as message passing and

277 views • 13 slides