Build a USB 2.0 device from scratch Friday 15, July 2016 Philmon - PowerPoint PPT Presentation

Build a USB 2.0 device from scratch Friday 15, July 2016 Philémon `PhilGekni` Gardet <phil@lse.epita.fr> 1 / 34

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Plan ● The Overview ● The Protocol layers ● Implementation considerations 3 / 34

The Overview 4 / 34

Host Topology RootHub 7 levels Host Hub Manages exchanges - Dev Hub Dev Hubs Dev - Plug / Unplug Dev Hub notifications Power management Dev - Dev Hub Hub Devices Dev Hub Hub - Offer functions Dev 5 / 34

Endpoints and pipes Device #? device Control endpoint 0 Basic types - Input Interface 1 Interface 2 - Output - Control In 1 In 2 Full-speed - 1 Control endpoint 0 Out 1 Out 2 - 15 in endpoints max - 15 out endpoints min Access by device + endpoint address 6 / 34

Endpoints/pipes types Interrupt transfer ( ≤ 64 Bytes) Isochronous transfer ( ≤ 64 Bytes) Regular queries Constant bandwidth Bulk transfer ( ≤ 1023 Bytes) Control transfers ( ≤ 64 Bytes) Large packet Device setup / Hubs management / Status Interrupt 5% Isochronous up to 69% Bulk 5% Control 7% Full-speed bandwidth 7 / 34

Class Base Descriptor Description Device Class ID Usage 00h Device Refer to Interfaces - Bass Class 01h Interface Audio - Subclass 02h Both Communication and CDC - Protocol 09h Device Hub EFh Both Miscellaneous FEh Interface Application Specific FFh Both Vendor specific 8 / 34

www.linux-usb.org/usb.ids Vendor ID / Product ID Device signature vid:pid Vendor ID Delivered by the USB-IF Product ID Chosen by vendor 9 / 34

The Protocol layers 10 / 34

Signals - The connector Name Voltage Domain Vcc 5 V D+ 3.3/0 V D- 3.3/0 V GND Ground 11 / 34

Signals - The link between a hub and a device 3.3V Hub Device 1.5K Ω D+ D D D- 15K Ω SE0 15K Ω SE0 OE OE D D D+ D+ D- D- Half-Duplex Full-speed link (D+ pull-up) 12 / 34

Signals - Decoding them - Differential level 13 / 34

Signals - Decoding them - NRZI encoding 0 1 1 0 1 0 0 0 1 1 1 0 1 1 Data NRZI 14 / 34

Signals - Decoding them - Bit stuffing 0 0 0 1 1 1 1 1 1 1 1 0 1 1 Data Stuffed Data NRZI 15 / 34

Signals - Patterns Sync / SOP EOP Reset Start of packet End of packet Idle K J K J K J K K D+ D- Full-speed: J=1 and K=0 2 bits 10-20 mS 16 / 34

Packets - A classical exchange Token package Data package Handshake package IN : Upstream IN : Downstream Upstream OUT : Downstream OUT : Upstream Timeout : 6.5 - 7.5 bit times (total window : 16 bit times) 17 / 34

Packets - PID/Types Token Handshake Data OUT ACK DATA0 IN NAK DATA1 SETUP STALL 1’ complement PID Check PID code code 4 bits 4 bits 18 / 34

Packets - The formats 8 bits 8 bits 7 bits 4 bits 5 bits 2 bits Dev Endpt Token packet SYNC PID CRC5 EOF addr addr Data packet SYNC PID Data CRC16 EOF 16 bits Ack packet SYNC PID EOF 19 / 34

Configuration - Descriptors Device descriptor Configuration Configuration descriptor descriptor Interface Interface Interface descriptor descriptor descriptor Endpoint Endpoint descriptor descriptor 20 / 34

Configuration - Descriptors data Class - Subclass - Protocol - VID - PID Device descriptor Max packet size endpoint 0 Configuration Power attributes - Max power descriptor Class - Subclass - Protocol Interface descriptor Alternative setting Endpoint Endpoint address - Endpoint type descriptor 21 / 34

Configuration - Device status - Attached - Powered - Default - Address - Configured 22 / 34

Configuration - Hub configured Internal hub registers updating 23 / 34 23

Configuration - Reset - Only one device - Adresse set to 0 24 / 34 24

Configuration - Set address - Only one device with 0 address - Host -> Endpoint 0 25 / 34 25

Configuration - Configure device - Gets Descriptors - Choses descriptors 26 / 34

Implementation considerations 27 / 34

Hardware role - Differential level - NRZI Payload SYNC EOF - Bit stuffing - Bit stuffing error detection 28 / 34

Internals Hold Rx Rx NRZI & Bit Shift Buffer RRDY stuffing register RACK TMT Tx NRZI & Bit Shift TRDY Buffer stuffing register Tx Hold ERR 29 / 34

Hold Internals Rx NRZI & Bit Shift Buffer D+ RRDY stuffing register Rx RACK D- TMT NRZI & Bit Shift TRDY Buffer stuffing register Tx Tx OE Hold SE0 ERR PLL_E D+ PLL Status Manager D- TOE RESET D- D+ 30 / 34

PLL and resynchronization - ALTPLL D+ - ALTPLL_RECONFIG “ Dynamic adjustment of the D- charge-pump current and loop- filter components to facilitate dynamic reconfiguration of the PLL bandwidth. This feature is available only in Arria GX, Sync pattern HardCopy II, Stratix II, Stratix II GX, Stratix III, and Stratix IV devices. “ 31 / 34

Deviation : PHY USB Microchip USB3320 32 / 34

Conclusion 33 / 34

Bibliography & links ● Universal Serial Bus Revision 2.0 specification Universal Serial Bus System Architecture ● ANDERSON Don, DZATKO Dave. Addison-Wesley, 2001 ● USB in a NutShell http://www.beyondlogic.org/usbnutshell ● USB class specifications http://www.usb.org/developers/docs/devclass_docs ● Open Sources PID/VID http://pid.codes/ 34 / 34