BUFFERS (PADS) DESIGN IN IC COMMUNICATIONS Venkata Reddy Kolagatla - PowerPoint PPT Presentation

INTRODUCTION TO IO BUFFERS (PADS) DESIGN IN IC COMMUNICATIONS Venkata Reddy Kolagatla Chip-Centre Chip-Centre, CDAC Bangalore

Topics Covered • Basic Block diagram of IO communication – Introduction to IOs • Buffered Vs Unbuffered • Introduction to RC circuits • Drive Strength Requirements of IC at particular speed with specified load • Typical Driver Architecture • OCD area dependency/crunch on pad • OCD design for different drive strengths • Process control of a driver • Basic Input buffer (Receiver) design Chip-Centre, CDAC Bangalore

Basic block diagram of IO Communication & Introduction to IOs Chip-Centre, CDAC Bangalore

Generic Diagram of IO communication (IC to IC Communication) Data generator package package Printed Wiring Buffers Receiver Board CMOS IC2 CMOS IC1 Chip-Centre, CDAC Bangalore

Introduction to IOs • Input/Output (IO) circuits enable a chip to communicate with the external world. • They are placed at the periphery of a chip and provide an interface between the chip and the external world. • As the internal circuitry grows in speed and efficiency, it processes data faster. • Matching IO circuits, in terms of speed and bandwidth, are critical to make sure that the processing power and efficiency of the internal circuitry or the core circuitry is best used. • The electrical signal outside the chip is unknown and possibly unsafe for the internal circuitry. • IOs help isolate the chip from such an environment and helps convert the external signal to a form where the internal circuit can process it. Chip-Centre, CDAC Bangalore

Types of IOs • The term ‘buffer’ is used alternately for “IO”, since IOs does not perform any logic operation on the signals!! • Depending on the type of application, IOs can be classified into different types. • Input • Output (2 states or 3 states) • Bi – directional Chip-Centre, CDAC Bangalore

Input Buffer V CC To Internal PAD circuitry VSS • The input buffer passes external data to the core. • It performs the level conversion from the external voltage to the core voltage level. • It helps improve the signal by performing some kind of signal conditioning. • ESD diodes associated with the input buffer help protect Integrated circuit (IC) chips from damage due to ESD events. Chip-Centre, CDAC Bangalore

Output Buffer V CC From Internal circuitry PAD From Internal circuitry VSS • The output buffer passes data from the core to the external world which is usually another component on the Printed Circuit Board (PCB) through a track. • It performs level conversion from the core level voltage to the IO level output voltage (the motherboard voltage level). • Output buffers can be either 2-state or 3-state depending on the application. For a 3-state buffer, the three states are logic low, logic high and high impedance. • A 3-state buffer will have an enable signal which facilitates achieving high impedance (Hi-Z) at the PAD • ESD diodes associated with the output buffer also help protect ICs from damage Chip-Centre, CDAC Bangalore due to ESD events.

Bi-directional Buffer V CC From Internal circuitry To Internal PAD circuitry From Internal circuitry VSS • A bi-directional buffer functions as both an input and an output buffer. • The enable signal which comes from the core determines if the buffer needs to be configured as an input buffer or an output buffer. • It is designed such that when enabled as an input buffer, the PAD is at a high impedance state. • There can be designs where both an input and an output buffer have separate enable signals. Chip-Centre, CDAC Bangalore

Buffered Vs Unbuffered Chip-Centre, CDAC Bangalore

Buffered Vs Unbuffered Characteristics Buffered Unbuffered Propagation Delay Low High Noise Immunity/Margin Excellent Good Output Impedance Constant Variable Output transition time Constant Variable Output oscillation for slow inputs Yes No Input Capacitance Low High Chip-Centre, CDAC Bangalore

Introduction to RC Circuits Chip-Centre, CDAC Bangalore

RC Circuit Chip-Centre, CDAC Bangalore

Low Pass RC – Circuit : Square Wave Input Chip-Centre, CDAC Bangalore

RC Charging Table – Low Pass RC % of maximum Time Constant RC Value Voltage Current 0.5 time constant 0.5T = 0.5RC 39.30% 60.70% 0.7 time constant 0.7T = 0.7RC 50.30% 49.70% 1.0 time constant 1T = 1RC 63.20% 36.80% 2.0 time constants 2.0T = 2.0RC 86.50% 13.50% 2.2 time constants 2.2T = 2.2RC 90% 10.30% 3.0 time constants 3.0T = 3.0RC 95.00% 5.00% 4.0 time constants 4.0T = 4.0RC 98.20% 1.80% 5.0 time constants 5.0T = 5.0RC 99.30% 0.70% Chip-Centre, CDAC Bangalore

If Period = 10RC Chip-Centre, CDAC Bangalore

If Period = 16RC Chip-Centre, CDAC Bangalore

If Period = 4RC Chip-Centre, CDAC Bangalore

Understanding it in frequency domain Chip-Centre, CDAC Bangalore

Understanding it in frequency domain Chip-Centre, CDAC Bangalore

High Pass RC – Circuit : Square Wave Input Chip-Centre, CDAC Bangalore

250.00 Drive Strength Requirement 200.00 150.00 Drive Strength( Ω ) R - calc if 4.4RC as T R - calc if 10RC as T 100.00 50.00 0.00 1GHz 1GHz 1GHz 1GHz 1GHz 2GHz 2GHz 2GHz 2GHz 2GHz 3GHz 3GHz 3GHz 3GHz 3GHz 4GHz 4GHz 4GHz 4GHz 4GHz 1pF 2.5pF 5pF 10pF 20pF 1pF 2.5pF 5pF 10pF 20pF 1pF 2.5pF 5pF 10pF 20pF 1pF 2.5pF 5pF 10pF 20pF Chip-Centre, CDAC Bangalore Speed with Load Cap.

Output Buffer/Driver/Transmitter Design Chip-Centre, CDAC Bangalore

Basic O/P Buffer - Architecture • O/p 0 -> 1 : depends on PUN (Pull Up Network) • O/p 1-> 0 : depends on PDN (Pull Down Network) • To ensure the loading doesn’t affect the internal data. • O/p drivers are large drivers that send a signal off chip (OCD). • The widths of these devices in the range of 400 to 1000um (L would be around 0.24u to 0.6u). • The size will depend on the frequency, power, voltage levels, current drive, functionality, etc.. of the buffer itself. • These large transistors must be laid out with great attention in detail, because the area that they will require is highly sensitive and they can directly affect the chip size. • The width of the bond pad o/p connection is based on many considerations : electro migration, resistance of the metal, impedance and inductance of the package connection, and equal load between the o/p transistors, among the all. • In general o/p buffers are supplied with special or isolated power lines that are not connected to any other transistors and are connected directly to independent power pads, issues in minimizing the power supply resistance to these transistors. Chip-Centre, CDAC Bangalore

Architecture of a Driver(O/P Buffer) Vccq Vccq C L = Bond pad C W = Bond wire cap cap + + Slew wire cap Via cap PU PU + + Self device cap layer cap + Data Pre Next IC’s i/p cap PAD Driver PVT C W C L PD PD Gnd Gnd Gnd Gnd Chip-Centre, CDAC Bangalore Current Design IC

Progressive Sizing – Pre Driver requirement • We cannot use a big inverter to drive a large output capacitance because, who will drive the big inverter • The signal that has to drive the output cap will now see a larger gate capacitance of the BIG inverter. • So this results in slow rise or fall times . • A unit inverter can drive approximately an inverter that's 4 times bigger in size. • So say we need to drive a cap of 64 unit inverter then we try to keep the sizing like say 1,4,16,64 so that each inverter sees a same ratio of output to input cap. • This is the prime reason behind going for progressive sizing. Chip-Centre, CDAC Bangalore

Drive Strength Calculations • Let us say 1.2v, with 1Gbps to drive 5pF load • Assume that a minimum of 25ohm drive strength is required • So, (*** R , Idrive , R α 1/width of the transistor α 1/Idrive ) 𝑊𝑑𝑑𝑟/2 1.2/2 𝐽 = = 25 = 24mA 𝑆 • Let us say per micron width of a transistor (for both Pmos & nmos), I = 48uA, total of 500u is required in pull up and in pull down to achieve 25ohm drive strength. • According to GDR(Geometric Design Rules), a transistor should not exceed a 10u(assume) width for a particular technology. • So we have to connect such type of transistors in parallel as many needed accordingly, in order to get the specified drive strength. Chip-Centre, CDAC Bangalore

Typical Driver Vccq PD M1 PU M5 M2 M6 M3 M7 M4 M8 IOx GND Chip-Centre, CDAC Bangalore

Typical Driver Design V CC From Internal 500u circuitry PAD From Internal 250u circuitry VSS Typically length would depend on the technology node – It is better to have maximum length such that it should have less leakage. Now -> PVT control ? -> tri-state control ? -> Design of diff. types of drive strengths? -> drive strength calculated at Vcc/2, why? Chip-Centre, CDAC Bangalore

Input Buffer/Receiver Design Chip-Centre, CDAC Bangalore