Bas Basic ic El Elec. ec. En Engr gr. . Lab Lab ECS EC S - PowerPoint PPT Presentation

Bas Basic ic El Elec. ec. En Engr gr. . Lab Lab ECS EC S 204 04/210 Dr. Prapun Suksompong prapun@siit.tu.ac.th Office Hours: BKD 3601-7 Tuesday 9:30-10:30 Friday 14:00-16:00 1

Lab 7  Operational amplifier  Inverting amplifier  Inverting Integrator 2

Op-Amp 741  OP erational AMP lifier V+ , Positive power supply O Noninverting (1) Offset null NC (8) (7) input (2) Inverting (3) V+ (7) (6) input (3) Noninverting + Output (6) (2) Output input (4) Inverting (4) V- Offset null (5) V- , Negative input power supply 3

Placing op amps on the proto-board  Plug in op amp chips so that they straddle the troughs on the proto board.  In this way, each pin is connected to a different hole set.   4

Powering the op amp  The op amp must be powered by O (1) Offset null NC (8) (2) Inverting voltage supplies. V+ (7) input (3) Noninverting + Output (6) input  These supplies are often ignored (4) V- Offset null (5) in op amp circuit diagrams for the sake of simplicity. Noninverting + input V cc (7) (3) - (6) + (2) (4) V cc Inverting - input 5

Part A: Inverting Am Amplif ifie ier R F +5 V R R 2 7 + 6 V i V o + 4 3 Sinusoid - 1 kHz -5 V R   F V V. o i R R 6

Part A: Inverting Am Amplif ifie ier R F +5 V R R + 2 7 V cc - V o 6 V i + + 4 V cc 3 Sinusoid - -5 V 1 kHz CH1 CH2 R   F V V. o i R R 7

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Part B: Inverting In Integ egrat ator or + v C -      i C i t i t C i C   R v t V+ d     i C v t o X R dt i in + v i t v o 1 +          v t v 0 v t dt - V- o o i RC 0 T   v t h i   h 2 h Zero-average input (DC offset = 0) Area = hT/2 1 T   h v t 9 RC 2 o

Inverting Integrator (2) + v C -      i C i t i t C i C   R v t V+ d     i C v t o X R dt i in + v i t v o 1 +          v t v 0 v t dt - V- o o i RC 0 T  An input with nonzero mean (DC offset) can saturate the op amp.   v t   i v t o 10

Inverting Integrator: AC SS Analysis + v C - i C C   Z   R C V+ V  V o i   R X i in +   v i V 1    v o + i      - R j C V-  The gain at f = 0 is unbounded. 11

Inverting Integrator w/ Shunt Resistor  In practical circuit, a large resistor R p is usually shunted across the capacitor R p   / / Z R   C p  V V C o i   R R V+   R V    p i   X     i in R j R C 1 + p v i v o + - V-  Observe that at f = 0, the gain is finite. 12

Inverting Integrator w/ Shunt Resistor  The output will not be R p triangular anymore. C  “Virtually triangular” if R V+ R p C >> T/2. X i in + v i v o + - V-    v t h i    Rp 1 r  v t h  o R 1 r   1     r exp   13 2 fR C   p