Audit of the BLM LHC system Beam loss interface to machine protection and energy distribution The BLECS combiner and survey card Functional test bench for the BLECF and BLECS Jonathan Emery 10 June 2008 1
Audit of the BLM LHC system Beam loss interface to machine protection and energy distribution Jonathan Emery 10 June 2008 2
Outline Overview Beam permit hardware Beam permit check Beam energy Audit of the BLM LHC system 3
Overview for one IP ● The BLM receive the energy through a redundant link from the CISV ● The beam permit signals, maskable and unmaskable, are send to the CIBUS with 2 redundant lines (A and B) A Timing A B CISV network B CIBUS Unmaskable Beam info Interlock BLM System network A B CIBUS Maskable Beam info Audit of the BLM LHC system 4
Beam permit signal path Crate 1 Daisy chain from TC1 to BLECS Measurements processing Beam permit U U U CH 1 BLETC BLETC BLETC BLETC BLECS N ° 1 N ° 2 N ° 16 Daisy chain from BLECS1 to CIBUS U M M M Processing and M threshold CH 16 UA UB MA MB comparison U U U BLETC BLETC BLETC Last BLECS N ° 1 N ° 2 N ° 16 M M M Measurement from the tunnel UA UB MA MB U nmaskable beam permit 3 to 4 crates per IP M askable beam permit CIBUS UBI Unmaskable U nmaskable B eam I nfo Interlock M askable B eam I nfo network CIBUS Maskable MBI Audit of the BLM LHC system 5
Beam permit daisy chain principle The FPGA provide a clock line to the „1‟ Retriggerable ● one-shot one-shot chip The CLR input is used to combine the CLR ● Beam permit line 2MHz signal from the previous card FPGA Retrig IN A pull-down resistor is used in case of a ● broken wire or a unwanted board Card 1 removal Same principle for the 2 links ● R Inside the crate (BLETC to BLETC) CLR to card 3 Between the crates (BLECS to BLECS) 2MHz FPGA Retrig IN Card 2 Audit of the BLM LHC system 6
Beam dump request time stamping A counter starts when the beam permit goes down, stops when the PM freeze ● trigger arrives. The CPU calculate the time stamp with the PM freeze arrival time and this counter (1 s accuracy). A status tells is the beam info had arrived after a dump request and gives the ● delay between this 2 events. BLECS Freeze Clk Turn counter Clk Bunch counter BLETC or BOBR Beam Start Counter dump to beam info BLECS permit Trig Counter dump to PM freeze Beam permit Beam info CIBUS 7 Audit of the BLM LHC system
Beam permit test procedure1 ● Tests the beam permit lines (BPL) inside the crate ● Tests the BPL between the crates (on the same IP) ● Test results are saved in the database Send the card number which 1 Energy link have to provoke the dump and U or M U U U BLETC BLETC BLETC BLECS 3 N ° 1 N ° 2 N ° 16 M M M last BLECS had received 2 the last dump request and notify all the other The BLECS provoke the BLECS Last BLECS dump which is transmitted All lines to „FALSE‟ to the last BLECS before the CIBUS CIBUS 8 Audit of the BLM LHC system
Beam permit test procedure 2 (proposal) Tests the BPL from the last crate to the CIBUS 1. Request from outside system (interlock system) to enter in test BLM system waits for the beam info to be „False‟ (U & M) 2. Enter in the test mode after a predefined time Then it is possible to force only one BPL (A or B) to „true‟ 3. 4. The BLM system return to normal state when the result is given to the BLECS The beam permits goes to normal operation state only if the test is successful Control of the BPL by an outside system only if the BLM system is in “test mode” The BLM system can only go to “test mode” if the beam info is “False” Only one line (A or B) can be “True”. The other one stay “False” Audit of the BLM LHC system 9
Beam energy The beam energy arrives from the timing system to the CISV located on the ● one crate of each IP (blmr) The CISV distribute the energy to all BLECS of the point (3 to 4 crates) in ● parallel through the cables between the crates. The integrity of the link is continuously checked and errors are counted and ● saved in the logging database. Conversion is done from 16bits to 5bits levels (32 levels of the BLM system). ● This conversion (linear) is hardcoded inside the FPGA of the BLECS A A Timing Last BLETC BLETC BLETC CISV network B B N ° 1 N ° 2 N ° 16 BLECS A A BLETC BLETC BLETC BLECS B N ° 1 N ° 2 N ° 16 B Audit of the BLM LHC system 10
Beam energy link New energy value every 100ms ● The energy frames are transmitted every ms ● (the energy value is repeated between new values) Uses a serial link, 1MHz bit rate, Manchester encoding ● The frame is 32 bits long and content: ● LHC energy header (“1001“) Spare bits (”000”) Error Toggle bit expected to have a transition every 100ms counters to Energy value (16 bits) the DB CRC (8 bits) A A Timing BLETC BLETC BLETC CISV network BLECS B B N ° 1 N ° 2 N ° 16 Audit of the BLM LHC system 11
Audit of the BLM LHC system The BLECS combiner and survey card Jonathan Emery 10 June 2008 12
Outline Hardware Crate overview Beam energy Beam permit High voltage control Voltages survey Tests Audit of the BLM LHC system 13
Hardware Based on DAB card ● Combiner features added => VME 64x => Stratix 40k Beam permit ● => SRAM memory => Daisy chain between crates => One site code update => Beam Interlock => Specific BI signals on P0 CIBUS interface Reuse of existing material ● Interface to high voltage PS ● => FPGA code for DAC for control VME ADC for monitoring Serial number chip Flash memory Monitoring VME PS ● => Flash programming for specific behavior (ripples) Crate interconnections for ● test of the BLM system Audit of the BLM LHC system 14
Hardware Interconnection between crates (1 to 4) Create 1 BLETC BLETC Beam permit: same connection between BLECS N ° 1 N ° 16 BLECS than between BLECS and CIBUS IC BLECF Last BLECS (before the CIBUS) control BLECF the HV but all can read the monitoring of IC Create 2 this voltage. BLETC BLETC BLECS N ° 1 N ° 16 IC BLECF Beam energy distribution from last crate IC BLECF to all the others Create n BLETC BLETC Last IC BLECF N ° 1 N ° 16 BLECS BLECF IC CIBUS Unmaskable Beam Permit CIBUS Maskable Beam Permit IC Ionization chamber HV1 + HV2 BLECF Tunnel card for acquisition BLETC Processing card BLECS Combiner card CIBUS Interlock interface HV High Voltage power supply Audit of the BLM LHC system 15
Crate overview Daisy chain of the beam permit lines (U and M) „1‟ Energy 5 bits to all BLETC BLETC BLETC BLETC BLETC CPU CISV BOBR N ° 1 N ° 8 N ° 9 N ° 16 + info Turn clk Triggers Energy 16 bits Acquisition and control BLECS Beam permit CIBUS Beam info Control High voltage Monitoring Audit of the BLM LHC system 16
Beam energy Serial reception with redundant channels (A and B) P0 Connector Continuous check for: Frame reception, CRC error, timeout frame, time out toggle bit 16 Beam Energy (Serial) BLETC Translation 16 bits to 5bits+1bit(error signal). Hardcoded conversion table Substitution of the original value by any value (in test mode only) Energy conversion & add information Additional information on the reminded free bits Serial transmission to the 16 TC receivers in parallel P2 Connector CISV Beam Energy (Serial) FPGA CRC error or CRC error or Toggle bit source used for the Action Comment timeout A timeout B timeout energy 0 0 0 A - Normal operation 1 0 0 B Increase counter CRC error A 0 1 0 A Increase counter CRC error B 1 1 0 - Previous beam energy value used Highest Energy “FFFF” x x 1 Increase counter Toggle bit timeout The timeout is 110% of the normal & error bit „1‟ time between the energy values Audit of the BLM LHC system 17
Beam energy CISV transmission specification 1. LHC energy header => "1001“ 2. ”000” Toggle bit time out check (errors counter) 3. Toggle bit 4. Energy value (16 bits) Energy value (16 bits) 5. CRC (8 bits) CRC check (errors counter) Conversion + additional information & control Beam Energy Error bit SofResetTC System Unmaskable Maskable Beam BPL Unmaskable test BPL Maskable Beam Permit (0 to 31) [1 bit] [1bit] under Beam Info [1 Info [1 bits] activation [1 bit] test activation Line test TC [5 bits] Test bits] [1 bit] Card Number [4 bits] Bit position [15..11] [10] [9] [8] [7] [6] [5] [4] [3..0] Broken link 31 (highest) 1 0 0 1 1 0 0 0 state* * Applied when both transmission are broken. Information Used to provoke beam dump from the CIBUS to TC individually (during test) BLECS transmission specification 1. ”10010000” header (8 bits) To 16 BLETC in parallel 2. Composite data (16 bits) 3. Toggle bit + ”000” (4 bits) 4. CRC (4 bits) Audit of the BLM LHC system 18
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