ASYMMETRICAL DOUBLE GATE (ADG) MOSFETs COMPACT MODELING M. Reyboz, O. Rozeau, T. Poiroux, P. Martin
2005 OUTLINE I INTRODUCTION II ADG ARCHITECTURE III MODELING DIFFICULTIES IV DIFFERENT WAYS OF MODELING V IMPLICIT ANALYTICAL MODEL: ITERATIVE RESOLUTION VI EXPLICIT ANALYTICAL MODEL: FULLY ANALYTICAL EXPRESSIONS VII CONCLUSION 2
2005 INTRODUCTION GENERAL CONTEXT WHY ARE WE INTERESTED IN MODELING ADG MOSFETs? • New Devices – classical CMOS technologies + PD SOI CMOS forecasts of the ROADMAP = ?? – New devices: FD SOI CMOS Bulk CMOS New devices GAA, FinFET, SON & planar DG 90 nm 65 nm 45 nm 22 nm • ADG MOSFET 2004 2007 2010 2016 – Excellent channel control – Design flexibility with a second gate independently driven • Model: to take advantage of this new device designers need a model • Compact Model: to design new circuits 3
2005 ADG ARCHITECTURE DIFFERENCES BETWEEN SYMMETRICAL (SDG) AND ASYMMETRICAL (ADG) DG MOSFETs V g1 Source Front gate y T ox1 Front oxide Front gate O L Channel Drain Source Silicon film Back gate Back oxide T ox2 T si Drain Back gate x PICTURE: ADG MOSFET V g2 M.Vinet et al, SSDM 2004 S CHEMATIC: DG MOSFET 22nm node The asymmetry of the structure: ! gate oxide thicknesses ! gate voltages ! or/and gate work functions 4
2005 MODELING DIFFICULTIES BASIC EQUATIONS OF ADG DRAIN CURRENT W V ∫ = µ d φ I Q d ds inv imref L V s BOUNDARY CONDITIONS GAUSS THEOREM c = − ψ ox E ( V ) s 1 ε g 1 s 1 = ε − Q ( E E ) si c inv si s 1 s 2 = − − ψ ox E ( V ) s 2 g 2 s 2 ε si POISSON EQUATION & ITS FIRTS INTEGRATION ψ 2 d q . n = ε 2 dx si ψ − φ ψ − φ 2 . q . u . n s 1 imref s 2 imref 2 − 2 = − t i E E exp exp s 1 s 2 ε u u si t t to calculate physical I ds , unknowns are ψ s 1 and ψ s2 5
2005 MODELING DIFFICULTIES MATHEMATICAL DIFFICULTIES ASYMMETRY Not always a minimum of potential in the silicon film: 2 CASES Band diagrams Ψ s2 Ψ s 1 Ψ s 1 Ψ s2 Ψ s 1 Ψ s 1 Ψ s2 E fermi i Ψ s2 ψ min ψ min FIRST DIFFICULTY DEFINE 2 CASES AND THEN UNIFY THEM 6
2005 MODELING DIFFICULTIES MATHEMATICAL DIFFICULTIES SECOND DIFFICULTY NO EXACT SOLUTIONS OF ψ s 1 AND ψ s2 2 OPTIONS MAKE PHYSICAL FLOATING NODE RESOLUTION ASSUMPTIONS 4 unknown parameters , Simplifications of ψ s1Source , ψ s1Drain & ψ s2Source , ψ s2Drain Poisson equation 7
2005 DIFFERENT KINDS OF MODELS DIFFERENT WAYS OF MODELING ! 1 st OPTION: IMPLICIT ANALYTICAL RESOLUTION Use of floating nodes or iterative resolutions to solve Poisson’s equation. ! 2 nd OPTION: EXPLICIT ANALYTICAL RESOLUTION Poisson’s equation is solved with physical approximations allow to get explicit formulations of electrical parameters fully analytical model. – Charge-based model – V th -based model 8
2005 IMPLICIT ANALYTICAL MODELING • MAIN ACTORS: 3 teams – Y. Taur (USA, University of California): mainly for SDG MOSFET – M. Chan (Hong Kong University of Science & Technology): ADG MOSFET – T. Nakagawa (Japan, AIST): ADG MOSFET ! Y. Taur, “ Analytical Solutions of Charge and Capacitance in Symmetric and Asymmetric DG MOSFET”, IEEE Trans. Electron Devices, vol.48, n°12, Dec. 2001. ! M. Chan, “Quasi-2D Compact Modeling for DG MOSFET”, NSTI Nanotech, vol.2, pp.108- 113, 2004. ! Nakagawa et al., “ Improved Compact Modeling for Four-Terminal DG MOSFETs”, NSTI Nanotech, 2004. 9
2005 IMPLICIT ANALYTICAL MODELING WHY ? COMPLEXITY of basic equations MANY ADVANTAGES No problem to unify the different operating modes PREDICTIVITY because basic equations could be solved for all materials and geometrical parameters ACCURACY because it keeps all basic equations without any (or with few) simplification 10
2005 IMPLICIT ANALYTICAL MODELING PRINCIPLE OF FLOATING NODE SOLUTION (Taur model) Minimum of potential Unknowns: ψ 0 and x 0 2 different modes No minimum of potential Unknowns: ≈ ψ S1 & ψ S2 2 UNKNOWNS + SOURCE & DRAIN SIDE 4 FLOATING NODES for each case Each mode should be NUMERICALLY solved thanks to BOUNDARY CONDITIONS. 11
2005 IMPLICIT ANALYTICAL MODELING PRINCIPLE OF FLOATING NODE SOLUTION (Taur model) DRAIN CURRENT I ds V 2 d W Q V ∫ = µ d φ = α − I Q d inv I . Q ds inv imref ds inv L 2 V s V s NUMERICALLY ANALYTICALLY (EKV METHOD) Not really true for ADG because of interface coupling: need a unification 12
2005 IMPLICIT ANALYTICAL MODELING PRINCIPLE OF FLOATING NODE SOLUTION (Taur model) Symmetrical case : VerilogA + Eldo simulator SDG : L=0.5µm, W=1.0µm, Tsi=10.0nm, Tox=1.2nm 0.8 2.5 12.0 (µS) Transconductance (µS) Vgs =0.6 to 1.2V mA ) 0.7 Drain current (µA) Vds =5mV 16.0 10.0 2.0 Transconductance Drain current ( 0.6 8.0 12.0 0.5 1.5 0.4 6.0 8.0 1.0 0.3 4.0 0.2 0.5 4.0 2.0 0.1 0.0 0.0 0.0 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Gate Voltage (V) Gate Voltage (V ) Asymmetrical case : VerilogA + Eldo simulator Currently: convergence problem 13
2005 IMPLICIT ANALYTICAL MODELING • LIMITS : - Convergence problems because of the 4 floating nodes . - Simulation time. • For that, we choose to developp an explicit analytical model with only 1 floating node: T° 14
2005 EXPLICIT ANALYTICAL MODELING • MAIN ACTORS: 2 teams – J. G. FOSSUM (USA, University of Florida) – G. Pei (USA, Cornell University) • TWO KINDS OF EXPLICIT ANALYTICAL MODEL – Charge-based model – V th model ! J. G. Fossum et al., “UFDG and Nanoscale FinFET CMOS Design and Performance Projections”, IEEE ICICT, 2005. ! A.V. Kammula et al., “ A long Channel Model for the Asymmetric DG MOSFET Valid in All Regions of Operation”, IEEE Southwest Symposium Mixed-Signal Design, pp.156-161, 2003. ! G. Pei, “A Physical Compact Model of DG MOSFET for Mixed-Signal Circuit Applications – Part1: Model Description”, IEEE Transac. On Electron Devices, vol.50, n°10, Oct. 2003. 15
2005 EXPLICIT ANALYTICAL MODELING ADVANTAGES OF AN EXPLICIT ANALYTICAL MODEL – Better physical understanding – Easier to use for circuit design because of speed and convergence whatever the number of transistors DISADVANTAGES OF AN EXPLICIT ANALYTICAL MODEL – Less accurate in moderate inversion – Difficulties to get well derivatives 16
2005 EXPLICIT ANALYTICAL MODELING CHARGE-BASED MODEL • Weak inversion for both interfaces V g1 DG = capacitor divider C ox Volume inversion ψ s 1 C C ψ = − si + si ( 1 ) V V s 1 + g 1 + g 2 C si 2 C C 2 C C Silicon film T si si ox si ox Volume current ψ s2 C C ψ = − + ( 1 si ) V si V s 2 g 2 g 1 + + 2 C C 2 C C C ox si ox si ox V g2 • Strong inversion for both interfaces I ds1 SI Silicon film SI = SI 1 + SI I I I Both channels are independent T si Surface current ds ds ds 2 SI I ds2 17
2005 EXPLICIT ANALYTICAL MODELING CHARGE-BASED MODEL One interface is in strong inversion and the other one in weak inversion. Asymptotic case : ψ s 1 → ∞ Second integration Boundary conditions thus exp(- ψ s 1 ) → 0 of Poisson’s equation = SI 1 + WI I I I ds ds ds 2 SI I ds1 Surface current T si Volume current I ds2 WI 18
2005 EXPLICIT ANALYTICAL MODELING CHARGE-BASED MODEL LIMITS : unification between different operating modes V g unification V ds unification CURRENT 2.10 -03 6.10 -6 10 -5 Atlas simulations Atlas simulations Model Model 10 -7 V g1 =1.2V 1.10 -03 4.10 -6 I d s (A ) V g2 =1.2V I ds (A) I ds (A) T si = 1 5nm V g2 from 0.1 to 0.3 V 10 -9 V ds = 5mV L=0.5µm 5.10 -04 V g1 =1.2V 2.10 -6 W= 1 µm V g2 =0.1V 10 -11 0 0 10 -13 0 0.2 0.4 0.6 0.8 1 1.2 0.1 0.3 0.5 0.7 0.9 1.1 V g1 (Volt) V ds (V) 1.10 -05 Atlas simulations Model 9.10 -06 8.10 -06 ! Unification problem when Vg2 is high. 7.10 -06 V g2 =1.2V I ds (A) V ds =5mV 6.10 -06 ! Problems to have a continuous 5.10 -06 4.10 -06 transconductance 3.10 -06 0.2 0.4 0.6 0.8 1 1.2 V g1 (V) V th -based model is developping: charge and current model take into account interface coupling 19
2005 EXPLICIT ANALYTICAL MODELING V th -BASED MODEL • ASSUMPTION: no current flows from a channel to the other one (checked by TCAD simulations) • PRINCIPLE: 1 DGMOS = 2 SGMOS in parallel Q inv = Q inv1 + Q inv2 I ds = I ds1 + I ds2 + INTERFACE COUPLING DESCRIPTION + CORRECTION FACTOR DEFINITION to well describe strong inversion UNIFICATION OF THE DIFFERENT OPERATING MODES 20
2005 EXPLICIT ANALYTICAL MODELING V th -BASED MODEL FRONT & BACK V th − C V ' V ' eq g 2 g 1 tanh C 2 . U ( ) = − − − Si t V ' V n 1 . V ' n . U . ln − th 1 th 10 1 g 2 1 t C V ' V ' eq g 2 g 1 C 2 . U Si t − C V ' V ' eq g 2 g 1 tanh C 2 . U ( ) = − − − Si t V ' V n 1 . V ' n . U . ln − th 2 th 20 2 g 1 2 t C V ' V ' eq g 2 g 1 C 2 . U Si t 21
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