13th - 14th December 2012 Liverpool, United Kingdom Arkadiusz Bukowiec Faculty of Electrical Engineering, Computer Science and Telecommunications Institute of Computer Engineering and Electronics University of Zielona Góra P OLAND
Introduction Petri Net Interpreted Colored Distributed Application Specific Logic Controller Architecture Synthesis Conclusion An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 2 Arkadiusz Bukowiec
YT1 P1 t1 XN1 P2 P3 t2 YV1 P4 XF1 t3 YT2 P5 XN2 t4 YV2 YV1 P6 P9 t5 XF1 t9 XF2 P7 P8 t6 YM P10 t7 XF4 YV3 P11 t8 XF3 An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 4 Arkadiusz Bukowiec
P1 t1 P2 P3 P – set of places t2 T – set of transitions P4 t3 F – set of arcs P5 M 0 – set of initial marking t4 P6 P9 t5 t9 P7 P8 t6 P10 t7 P11 t8 An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 6 Arkadiusz Bukowiec
YT1 P1 Extension for information t1 XN1 exchange P2 P3 t2 Additional binary signals YV1 P4 XF1 t3 X – set of input variables YT2 P5 XN2 t4 Y – set of output variables YV2 YV1 P6 P9 Z – set of internal variables t5 XF1 t9 XF2 P7 P8 t6 YM P10 t7 XF4 YV3 P11 t8 XF3 An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 7 Arkadiusz Bukowiec
YT1 P1 Colors assigned to places and t1 XN1 transitions P2 P3 t2 Each color determine YV1 P4 50% 50% XF1 t3 State-machine subnet YT2 P5 50% 50% XN2 t4 Sequentiaql process YV2 YV1 P6 P9 50% 50% t5 XF1 t9 XF2 P7 P8 t6 YM P10 50% 50% t7 XF4 YV3 P11 50% 50% t8 XF3 An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 8 Arkadiusz Bukowiec
Architecture
YT1 P1 t1 XN1 P2 P3 t2 YV1 P4 50% 50% t3 XF1 YT2 P5 50% 50% XN2 t4 YV2 YV1 P6 P9 50% 50% t5 XF1 t9 XF2 P7 P8 t6 YM P10 50% 50% t7 XF4 YV3 P11 50% 50% t8 XF3 An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 10 Arkadiusz Bukowiec
No global clock signal Independent, local clock signals for each subcicuit Different methods of communication (synchronization) Handshake-based FIFO-based Controller-based Lookup-based Buffer-based An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 11 Arkadiusz Bukowiec
YT1 P3 P1 P2 t2 t1 XN1 MP1 P2 t2 t5 XF1 P3 YV1 P7 P4 XF1 t6 t3 YT2 YM P7 P5 P10 XN2 t4 t7 XF4 YV1 YV3 P6 P11 t5 XF1 t8 XF3 SMN 1 SMN 2 YV2 P9 t9 XF2 P8 P8 t6 MP2 t8 XF3 SMN 3 An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 12 Arkadiusz Bukowiec
SMN 1 X 1 Y 1 X D 1 Q 1 Y CC 1 RG 1 Y 1 X Z D D Q Q 1 Y Z Q Y Z 1 X Z SMN 2 X 2 Y 2 X D 2 Q 2 Y CC 2 RG 2 Y 2 2 X Z D D Q Q Y Z Y X Q Y Z 2 X Z Z SMN I X I Y I X D I Q I Y CC I RG I Y I X Z D D Q I Q Y Z Q Y Z I X Z An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 13 Arkadiusz Bukowiec
Synthesis method
Decomposition into state machime subnets Constructing the set of synchronizing variables Places encoding Forming conjunctions and formulas Creating decoder memory blocks Forming logic circuit An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 15 Arkadiusz Bukowiec
All places colored by first color creates first state machine subnet All the subsequent subnets are created in a similar way, except that all the sequences of places, which have already been placed in one of the previously created subnets are replaced by a macroplace An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 16 Arkadiusz Bukowiec
YT1 YT1 P1 P1 t1 XN1 t1 XN1 P2 P3 P2 P3 t2 t2 t2 YV1 YV1 P4 50% 50% P4 MP1 XF1 t3 XF1 t3 t5 XF1 YT2 YT2 P5 50% 50% P5 P7 XN2 t4 XN2 t4 t6 YV2 YV1 YV1 YV2 P6 P9 50% 50% P6 P9 YM t5 XF1 t9 XF2 P10 t5 XF1 t9 XF2 t7 XF4 P7 P8 P8 YV3 t6 P11 t6 t8 XF3 YM P10 50% 50% MP2 t7 XF4 t8 XF3 YV3 P11 50% 50% t8 XF3 An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 17 Arkadiusz Bukowiec
If a transition belongs to more that one state machine subnet, then transition input place in each subnet have to generate additional synchronization signal The fire condition of this transition in each subnet have to be extended by logical conjunction of signals generated by other subnets An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 18 Arkadiusz Bukowiec
YP3 YT1 P1 P3 t1 XN1 t2 XP2 YP2 YV2 P2 P9 MP1 t2 XP3 t9 XF2 t5 XF1 YP8 YV1 YP7 P8 P4 P7 t6 XP7 XF1 t3 t6 XP8 YT2 YM MP2 P5 P10 t8 XF3 XN2 t4 t7 XF4 YV1 YV3 P6 P11 t5 XF1 t8 XF3 An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 19 Arkadiusz Bukowiec
Minimum length code Separately for each subnet The place that belongs to initial marking receive code equal to 0 If there is no such place the code equal to 0 is assigned to a double macro place of such place An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 20 Arkadiusz Bukowiec
Separately for each subnet Conjunction describing place is formed with literals from the code of this place Conjunction related to a transition is formed using the conjunction of its input places and its guard condition Conjunction describing place hold condition is formed as conjunction of this place conjunction and negated disjunction of all conjunctions of its output places An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 21 Arkadiusz Bukowiec
Separately for each subnet Created based on D flip-flop equation Denoted as An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 22 Arkadiusz Bukowiec
Separately for each subnet Described as Truth table Logic equations Code of place forms address Output variables forms word Only output variables controlled by considered subnet are taken An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 23 Arkadiusz Bukowiec
Each subnet described as separate module Described in HDL Combinational circuit is described with the use of continues assignments Register memory described as D flip-flop Decoder described as process with case statement An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 24 Arkadiusz Bukowiec
Petri net allows an easy description of parallel processes GALS architecture allows distribution of the system The synchronization is made via buffers Proposed architecture and synthesis method is dedicated for FPGA devices An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets 26 Arkadiusz Bukowiec
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