Architecture Comparison for Concurrent Multi-Band Linear Power - PowerPoint PPT Presentation

Architecture Comparison for Concurrent Multi-Band Linear Power Amplifiers Zhen Zhang, Yifei Li, and Nathan M. Neihart Iowa State University MWSCAS 2015 – Fort Collins, CO

Outline  Motivation  Theoretical Comparisons  Efficiency  Linearity  Area  Conclusions 08/05/15 2

Motivation  Multiband radio is a basic requirement for today’s wireless devices  Current 4G standards propose carrier aggregation Then  Intra-band and inter-band  Contiguous and non-contiguous 1300 MHz GSM 850 MHz LTE GSM 1900 MHz UMTS GSM CDMA-2000 Now WiFi 400 MHz EDGE 800/900 MHz Diversity Band 1 2200 MHz EDGE 1800/1900 MHz 4000 MHz Diversity Band 2 UMTS 2100 MHz Diversity Band 3 UMTS 1900 MHz Diversity Band 4 AWS 1700 MHz UMTS 850 MHz GPS Band 1 UMTS 900 MHz GPS Band 2 LTE Band 13 LTE Band 17 WLAN 2 GHz LTE Band 20 WLAN 5 GHz LTE Band 25 3100 MHz 08/05/15 3

Motivation iPhone 5 mother board PA Modules Each IC contains several separate power amplifiers  Current approach consists of packing ever more separate PAs into a device  Large area  Complex signal routing  Complex control  Such architectures do not inherently support simultaneous multi-band signals  In light of this, researchers are now beginning to develop simultaneous multi-band PA architectures 08/05/15 4

Motivation  There are two primary approaches for realizing concurrent multi-band PAs Parallel Single-Band OMN  Multiple parallel single-band PAs P IN1 @ f 1 IMN M 1 P 01 + P 02 + … + P 0M OMN +  Larger area P IN2 @ f 2 IMN M 2  Must have some way of combining OMN the output signals P INM @ f M IMN M M  Single multi-band PA  Fewer components Concurrent Multi-Band  Theoretical drop in efficiency Multiband P 01 + P 02 + … + P 0M OMN P IN1 @ f 1 + IMN  Which approach is “better”? M 1 P IN2 @ f 2 P INM @ f M 08/05/15 5

Efficiency Comparison  Drain efficiency is defined as: 𝑄 𝑀 – Power delivered to the load 𝑸 𝑴 𝜽 = 𝑄 𝐸𝐷 – Power consumed from the DC supply 𝑸 𝑬𝑫  Multi-band output power is defined to be the total power in ALL DESIRED bands 𝑸 𝑴 = 𝑸 𝒈𝟐 + 𝑸 𝒈𝟑  Assuming a linear device and 2 bands, the drain current is: Single Stage in Parallel Single-Band 𝑱 𝑬,𝑸𝑻 = 𝑱 𝑬𝑫,𝑵 + 𝒋 𝒔𝒈,𝑵 𝒅𝒑𝒕 𝟑𝝆𝒈 𝑵 𝒖 + 𝜾 𝑵 Load Current of single stage Concurrent Multiband 𝑱 𝑬,𝑵𝑪 = 𝑱 𝑬𝑫 + 𝒋 𝒔𝒈 𝒅𝒑𝒕 𝟑𝝆𝒈 𝟐 𝒖 + 𝒋 𝒔𝒈 𝒅𝒑𝒕 𝟑𝝆𝒈 𝟑 𝒖 + 𝜾 Load Current 08/05/15 6

Efficiency Comparison 2-Band Parallel Architecture  The drain current swing is fixed 1 Drain Current (A) such that 𝟏 ≤ 𝑱 𝑬 ≤ 𝟐 0.5  Parallel, single-band architecture 0 0 1 2 3 4 5 2-Band Concurrent Architecture  Class A: 𝑗 𝑠𝑔,𝑁 = 0.5 and 𝐽 𝐸𝐷 = 0.5 1 Drain Current (A)  Class B: 𝑗 𝑠𝑔,𝑁 = 1 and 𝐽 𝐸𝐷 = 0  Class C: 𝑗 𝑠𝑔,𝑁 = 1.25 and 𝐽 𝐸𝐷 = -0.25 0.5 0  Single, multi-band architecture 0 1 2 3 4 5 Time (sec)  Numerical methods are used to set 𝑗 𝑠𝑔 Parallel Single and 𝐽 𝐸𝐷 for each class of operation Single-band Multi-band Class-A 50 % 25 %  Sweep 𝒈 𝟑 /𝒈 𝟐 from 1 to 10 Class-B 78.5 % 62 % Class-C 82 % 71 % 08/05/15 7

Efficiency Comparison  Efficiency can be increased by slightly overdriving the amplifier  Non-linear model presented in RF Power Amplifiers for Wireless Communication by S. Cripps is used for this investigation 𝟑 𝒖 − 𝟑𝑾 𝑯 𝟒 𝒖 𝑱 𝑬 𝒖 = 𝟒𝑾 𝑯  Parallel, single-band architecture Strongly Weakly Strongly Nonlinear Nonlinear Nonlinear 𝑾 𝑯 𝒖 = 𝑾 𝑬𝑫 + 𝒘 𝒔𝒈 𝒅𝒑𝒕 𝟑𝝆𝒈 𝑵 𝒖 + 𝜾 𝑵 1 Normalized Drain Current (A)  Single, multi-band architecture 0.8 0.6 𝑾 𝑯 𝒖 = 𝑾 𝑬𝑫 + 𝒘 𝒔𝒈 𝒅𝒑𝒕 𝟑𝝆𝒈 𝟐 𝒖 + 𝒘 𝒔𝒈 𝒅𝒑𝒕 𝟑𝝆𝒈 𝟑 𝒖 + 𝜾 Class A 0.4 Class B/C  𝒘 𝒔𝒈 and 𝑾 𝑬𝑫 are set such that 0.2 𝟏 ≤ 𝑾 𝑯 𝒖 ≤ 𝟐 0 -0.5 0 0.5 1 1.5 Normalized Input Voltage (V) 08/05/15 8

Efficiency Comparison 60  Compressed drain efficiency for Parallel, single-band Class A DE (%) parallel single-band power amplifier 50  Class-A: 𝜃 𝑏𝑤𝑓 = 56% 40 Single, multi-band  Class-B: 𝜃 𝑏𝑤𝑓 = 80% 30 2 4 6 8 10  Class-C: 𝜃 𝑏𝑤𝑓 = 84% 90 Parallel, single-band Class B DE (%)  Compressed drain efficiency for 80 single multi-band power 70 amplifier Single, multi-band 60  Class-A: 𝜃 𝑏𝑤𝑓 = 31% 2 4 6 8 10  Class-B: 𝜃 𝑏𝑤𝑓 = 67% 90 Parallel, single-band  Class-C: 𝜃 𝑏𝑤𝑓 = 75% Class C DE (%) 85 80  Outputs are ideally filtered to remove 75 Single, multi-band all non-linear distortion at the LOAD 70 2 4 6 8 10 Frequency Radio f 2 /f 1 08/05/15 9

Efficiency Comparison 1 Drain Current (A)  There is a significant drop in efficiency in the single, multi-band 0.5 architecture 0  Class-A: Reduction of 25% 0 1 2 3 4 5  Class-B: Reduction of 13% 1 Drain Current (A)  Class-C: Reduction of 9 % 0.5  This is due to the reduced power 0 0 1 2 3 4 5 in each band Time (sec)  This is improved by overdriving the 0.5 0.5 0.5 0.5 amplifier  Variation in efficiency as a 0.25 0.25 function of frequency ratio can be predicted by the peak-to-average- ratio of the input  Lower PAR leads to higher drain DC f L f H Freq. DC f L f H Freq. efficiency Single, multi-band Parallel, single-band 08/05/15 10

Linearity Comparison  Linearity is especially critical in concurrent multi-band systems  Parallel, single-band architecture  Nonlinear distortion causes harmonic generation only  Linearity of diplexer may be an issue  No limitations on frequency separation  Single, multi-band architecture  Nonlinear distortion causes harmonic AND intermodulation components  Restrictions on frequency choices  Becomes much more complicated for larger number of bands  Both cases will require good filtering at the output  Filtering in the parallel, single-band case will depend on the diplexer 08/05/15 11

Area Comparison  Component count can be a good indication of board area V DD Component Count for Parallel V B Single-band Architecture Component OMN Count IMN M 1 Input L-Match 2M P 01 + P 02 + … + P 0M OMN + Output L-Match 2M IMN M 2 RF Chock 2M RF Bypass 2M OMN Power Transistor M IMN M M Power Combiner 1 Total 9M+1 * M is the number of supported bands 08/05/15 12

Area Comparison  To now we have assumed ideal summation of the output signals  Practical implementations will use diplexer Insertion Practical Ref. Area V DD Loss summation block V B cannot be ignored 2 × 1.3 mm 2 TDK 202690DT ~0.4 dB 2-bands OMN 1 × 0.5 mm 2 TDK 105950DT ~0.5 dB 14 × 8.2 mm 2 Zou et al., MWCL 2012 ~0.5 dB IMN M 1 Dai et al., ICMMT OMN + 3 × 4 mm 2 ~0.5 dB 2012 IMN 3-bands M 2 Chongcheawchamnan 55 × 31 mm 2 ~3.4 dB et al., MWCL 2006 OMN Hayati et al., TMTT 90 × 90 mm 2 ~3.5 dB IMN M M 2013 08/05/15 13

Area Comparison Component Count for Single, Multi- V B band Architecture Component OMN Count Input L-Match 2M IMN M 1 Output L-Match 2M RF Chock 2 RF Bypass 2 Power Transistor 1 Power Combiner N/A Total 4M+5 * M is the number of supported bands 08/05/15 14

Area Comparison  Area is further compared using an example implementation  Assume a lumped-element implementation of both architectures  Assume dual-band support  20% added to account for routing Parallel Single-Band Single Multi-Band Area/ Component Num. of Num. of (Technology) Area Area Components Components Inductor/Capacitor 0.125 mm 2 / 8 1 mm 2 8 1 mm 2 (Matching (0201) Network) 4 2 mm 2 2 1 mm 2 0.5 mm 2 /(0402) RF Choke Inductor RF Bypass 4 124 mm 2 2 62 mm 2 31 mm 2 /(2917) Capacitor 36 mm 2 / 2 72 mm 2 1 36 mm 2 Power Transistor Cree GaN FET 40 mm 2 /Ave. 2- 1 40 mm 2 0 Diplexer band diplexers Total 19 286 mm 2 13 120 mm 2 08/05/15 15

Conclusions  Two popular power amplifier architectures for supporting concurrent multi-band signaling have been compared  Efficiency  Parallel, single-band architecture  Much higher efficiency for class-A  Gap is reduced for class-B and – C  Additional reduction in efficiency due to diplexer  Single, multi-band architecture  Reduced output power, per band, for the same DC bias  Efficiency depends upon frequency ratio as well as initial phase offset  Linearity  Parallel, single-band architecture  Essentially the same linearity requirements as traditional single-band amplifiers  Single, multi-band architecture  Significant harmonic and inter-modulation distortion  Limits the choice of frequency bands  Becomes more severe as the number of supported bands increases 08/05/15 16