Architectural Aspects in Design and Analysis of SOT- based Memories Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril & Mehdi Tahoori INSTITUTE OF COMPUTER ENGINEERING (ITEC) – CHAIR FOR DEPENDABLE NANO COMPUTING (CDNC) KIT – University of the State of Baden-Wuerttemberg and www.kit.edu National Research Center of the Helmholtz Association
Outline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For various memory technologies System-level Summary & Conclusion ASPDAC-2014 2 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Outline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For various memory technologies System-level Summary & Conclusion ASPDAC-2014 3 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Memory Hierarchy High Performance & Endurance High Leakage, Scalability Issue SRAM and Radiation Vulnerable Refresh, Scalability Issue and DRAM Destructive read Endurance, Scalability Issue FLASH and Radiation Vulnerable DISK High Capacity A Universal Memory Required to overcome these limitations Non Volatile Magnetic RAM is promising candidate ASPDAC-2014 4 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Motivation STT-MRAM has Separate potential to become Perpendicular Read & Write Anisotropy universal memory current Path technology However, obstacles are Spin Transfer Torque High write current & time “Read Disturb” Addressed using Spin Spin Orbit Orbit Torque (SOT) Torque Results in Low Write Current Low Switching Time Avoid Read Disturb ASPDAC-2014 5 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Outline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For various memory technologies System-level Summary & Conclusion ASPDAC-2014 6 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Basics of Spin Transfer Torque (STT) Free Layer Barrier Oxide Layer, MgO Reference Layer Parallel Magnetisation (P) Anti- Parallel Magnetisation (AP) Low Resistance High Resistance Two ferromagnetic layers seperated by a oxide barrier layer Magnetic Tunneling Junction (MTJ) Cell is a storing device Value stored as a resistance state ASPDAC-2014 7 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Bit-cell using STT based MTJ cell Bit-cell has three terminals: Bit-Line Word-Line Source-Line Read current is unidirectional Read & Write Write current is bidirectional Current Path Word-Line Possible “Read Disturb” Source-Line Same path for read and write ASPDAC-2014 8 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Merits & Demerits of STT Merits: Low Read Latency High Density High Endurance Non-Volatility High Retention Scalability Radiation Immune CMOS Compability Demerits: High Write Power Aditional Layer requires High Write Latency Read Disturb ASPDAC-2014 9 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
In-Plane Vs Perpendicular Anisotropy Parameters In-Plane Magnetic Perpendicular Anisotropy Magnetic Anisotropy Diagram 𝛽 𝛽 𝜃 × 1 + H d Ratio of critical switching 𝜃 current to thermal stability, 2H k I C ∆ where, 𝛽 = damping constant, 𝜃 =STT efficiency, H d = demagnetization field, H k =in-plane anisotropy field switching current High Low switching time More Less Perpendicular magnetic anisotropy Low switching current Less switching time “Read Disturb“ still remains challenge ASPDAC-2014 10 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Spin Orbit Torque Separate read and write current paths One additional terminal No read disturb Need not to maintain ratio of Read I Read I Write Current Path Write Current Path Less current required to flip Word-Line due to parallel magnetization Source-Line Fast switching ASPDAC-2014 11 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
STT-MRAM VS SOT-MRAM Parameter STT-MRAM SOT-MRAM Bit-cell Terminals 3 4 (1T1MTJ type) Access Transistor 8F 2F Current (uA) 750 100 Write Current Period (ns) 11 0.3 Read Disturb High Probability Almost Nil Read Energy (pJ) 1.8 1.8 Write Energy (pJ) 3.9 (reset)/3.4(set) 0.1 Switching Behavior Asymmetrical Almost Symmetrical Magnetic Anisotropy In-Plane Perpendicular ASPDAC-2014 12 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Tool Simulation Flow 1 CMOS SOT Circuit-Level SPICE Model Model Bit-Cell Characteristics Memory Memory NVSIM Configuration Architecture-Level Processor System-Level Configuration GEM5 ASPDAC-2014 13 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Basic Memory Architecture Word-line drives the access transistor of bit- cell Write Enable =1, for write operation Write Enable =0, for read operation ASPDAC-2014 14 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Simulation models STT-MTJ SPICE modelling framework presented in [ W. Guo, JAP-2010] SOT-MTJ Compact Verilog-A framework presented in [ K. Jabeur, IJESE-2013] CMOS General purpose TSMC 65nm models. ASPDAC-2014 15 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Tool Simulation Flow CMOS SOT Circuit-Level SPICE Model Model 2 Memory Memory NVSIM Configuration Architecture-Level Memory Characteristics Processor System-Level Configuration GEM5 ASPDAC-2014 16 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
NVSIM flow Architecture related Information like Cell related Information like Type of Memory Cell Type Following modification done: Capacity Cell Area & Aspect Ratio Data Width Cell information On & Off Resistance Local & Global Wire Type Read power Memory architecture information Routing Type Set & Reset Current Optimization Type Set & Reset time Enable the asymmetrical write behavior Array Organization Set & Reset Energy Design Constraint Access transistor Width Switch for CACTI assumption Hierarchy Reports for given Memory Configuration ASPDAC-2014 17 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Tool Simulation Flow CMOS SOT Circuit-Level SPICE Model Model Memory Memory NVSIM Configuration Architecture-Level 3 Processor System-Level Configuration GEM5 Performance Number ASPDAC-2014 18 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Input & Output Parameters Input Processor Memory Applications Parameters Configuration design data Extended GEM5 to support MRAM Changed uniform read- GEM5 Simulator write latency to non- uniform Leakage Static Runtime Power Performance Energy Runtime • Access numbers Access Output Per Access • Dynamic Hit/Miss rate Numbers Parameters Energy • Energy Instruction-per- cycle NVSim GEM5 ASPDAC-2014 19 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Outline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For various memory technologies System-level Summary & Conclusion ASPDAC-2014 20 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Comparison of various Memory Technologies Parameters SRAM NAND STT- SOT- PC- R- FLASH MRAM MRAM RAM RAM Area [ mm 2 ] 2.8 0.2 1.6 1.5 0.3 0.7 Read Latency [ns] 2.2 565 1.2 1.13 0.6 1.2 2 × 10 5 Write Latency [ns] 2.0 11.2 1.4 150 21 Read Energy [pJ] 587 3921 260 247 363 193 Write Energy [pJ] 355 6902 2337 334 63670 592 Leakage [mW] 932 77 387 254 153 115 Values are extracted using NVSim for 512 Kbyte capacity Latency optimization ASPDAC-2014 21 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Area Comparison for various memory sizes STT & SOT are better with capacity increase SRAM is better Voltage sense amplifier used for SRAM High current drivers for STT and SOT SOT built on STT framework with different access transistor size ASPDAC-2014 22 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Read & Write Latency Comparison SRAM varies linearly with capacity increase STT & SOT, remain almost flat with capacity increase ASPDAC-2014 23 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Energy Comparison SOT has almost same read & write access energy ASPDAC-2014 24 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
Leakage Comparisons SRAM varies linearly with capacity increase STT & SOT, leakage is due to periphery circuits ASPDAC-2014 25 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM
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