An Integrated Modeling, Synthesis and Verification Methodology - PowerPoint PPT Presentation

HLS Based HW and SW Co-Design of Complex IP Subsystems An Integrated Modeling, Synthesis and Verification Methodology Xiaojian Liu Greg Smith June 4th, 2013 David Hansen Jeff Wong Louie Lee PAGE 1

2 Author Page • Xiaojian Liu, xiaojian@qti.qualcomm.com • Greg Smith, smithg@qti.qualcomm.com • David Hansen, hansend@qti.qualcomm.com • Jeff Wong, wjeff@qti.qualcomm.com • Louie Lee, louielee@qti.qualcomm.com • Affiliation: Qualcomm Inc.

3 Outline • SoC and IP Design Challenges • Mastering Complex IP Subsystem: HW and SW Co-Design • Key to HW & SW Co-Design: HL Modeling & Synthesis • HL Modeling, Synthesis & Optimization: From Transaction Accuracy to Cycle Accuracy • Verification & Validation: Moving to High Level • Key to Design Productivity: An Integrated HL Design Flow • Design Examples • Remarks

4 SoC and IP Design Challenges • SoC capacity still increasing • Requirements for additional features continues to grow • Complex IP Subsystem itself is a “ deeply ” embedded system with hardware and software • HW/SW Co-Development • IP subsystem Design Team is typically “small” compared to a full SoC design team SoC and IP SS C-Bus Video Video Audio Video IO CPU GPU Post- Camera Modem Codec Proc Display Interface Proc D-Bus

5 Master Complexity at IP Subsystem Level - HW/SW Co-Design • IP design requires a different design approach: a “high performance” and “high efficiency” HW and SW co -design methodology, on a “ closed ” platform. IP Algo IP Arch HW Design SW Design Virtual Platform

6 Key to HW & SW Co-Design: HL Modeling & Synthesis • Models: • Hardware (datapath and micro-processors) • Software (control and datapath processing) • Virtual Platform (transactional connectivity) • High Performance: • Must use high level (C) hardware model for fast simulation speed • Must use high level (C) virtual platform for fast simulation speed • Must use high layer (C) software code for fast simulation speed • High Efficiency = Automated Design Flow (HL to LL): • High level (C) model must be synthesizable to RTL and below • Virtual platform must support multi-level of modeling accuracy: functional, multi-level transactional, and cycle accuracy • High layer SW (C) code must interface with low layer driver code and higher layer App code seamlessly

7 HL Modeling, Synthesis & Optimization IP Algo USE (unified software environment): Multi-layer seamless context aware IP Arch C2RTL synthesis interface PPA optimization HL/CA verification Functional Ref. C Model Transactional FEC SW Multi-Level Transactional SS Platform Synth C Blk / Blk Driver & uP Descript. API RTL Platfm Platform VIP library Platfm Driver Blk Design ML TL modeling RTL SS HL/TL verification Platform RTL SS Platfm API Integration

8 High Level Synthesis & Optimization: An Enabling Technology Process Independent; Sequential Clock Gating; Scheduling; Memory Gating; Resource Sharing; Vt and Power Domain Aware; Top-down Hier. Synthesis Power Estimation; Bottom-Up Synthesis; ECO C++/SystemC/RTL; Area/Timing Estimation; TLM TV Untimed C to RTL Synthesis & RTL synth “C” PPA Optimization RTL TC ISS uP uProcessor Synthesis Description Compiler

9 High Level Synthesis & Optimization: -- From Transaction Accuracy to Cycle Accuracy • “ Forward ” Synthesis TS TS TS TS • Untimed (synth) “C” design TS/TLM TS/TLM • Scheduling - > “timed” design TS TS TS TS • Logic optimization -> RTL design • Adding RTL “ transactors ” -> RTL interfaces/ports/channels • -> Building blocks for RTL SS design • “ Backward ” Analysis • Add HL (SysC ) “ transactor ” to “untimed” C design • Add TLM wrapper to the top HL “ transactor ” if required • -> Building blocks for ML Transactional SS performance modeling • “ Feedback ” Loop • Micro-architecture optimization • Performance analysis • Hardware verification • Software validation

10 Verification & Validation: Moving to High Level • Subsystem Level Input Stimulus - Fast to build & to run Functional - Support iterative design Ref. C Model SW approach Multi-Level - Support ML transactions Transactional SS Platform Synth C Blks Driver & API Test Vectors - Simplify RTL TB environm. - Seamless integration with RTL Datapath existing RTL methodology Platfm Driver Design - Traffic performance analys. RTL SS Platform uP RTL Design Platfm API

11 Verification & Validation: Moving to High Level Automated RTL P/F and Cov Verification • Block Level RTL Simulator Transactors Offline RTL C Testbench Coverage Model Ref C Synth C C2RTL Synthesis RTL Code Model Model C Inline Coverage Model Transactors C Simulations P/F and Cov Transactional C2RTL FEC Relevant observation points are always either in IO Automated C2RTL library or as C variables Transactional FEC

12 An Integrated HL Design Methodology: Key to High Design Productivity • Block Level Algorithm Algo Design Evaluation uP ISS ISA Model Verification AlgoC Model Architecture eAlgo Ref C uP RTL uP RTL HW/SW SW Model Core Verification Partitions SynC uP ISA Model Model Synth Synth RTL RTL VC Verification Core Model RefC/SynC Verification IPQ IP Charac- Validation terization An integrated algo design & IP Tuning & hw/sw modeling U.C. Test process Design Modeling Synthesis Verification

13 An Integrated HL Design Methodology: Key to High Design Productivity • Subsystem Level C Cov Model RTL Cov Model Syn C Ref C C2RTL Design Synthesis Design RTL Design timing power TLM Transactor Wrapper IP SS Virtual SoC Platform Other TLM Virtual IP models Platform Traffic System System SW SW Dev Performance Validation Dev Analysis

14 Design Examples Hand Ref C Synth C Speed Design Area RTL Area Power LoC LoC (MHz) LoC 1263 1794 51.72 5152 51.26 266 Block1 Block2 1954 3722 296,436 10988 371,855 400/200 4281 12578 686,567 38110 400 Block3 3155 9498 774,726 28780 400 Block4 Block1: apple to apple comparison using the same micro-architecture Block2: HLS design uses micro-architecture optimization to increase the clock speed and decrease the area while keeping the same throughput Block3,4: LoC for Hand RTL is extrapolated (3x). It is beyond a single designer’s reach within a reasonable time period

15 Remarks • Moving to High Level (C) design provides significant efficiency and effectiveness. • High Level Synthesis tool is an enabling technology, upon which an integrated high level design flow can be built. • An integrated high level design flow includes h/w and s/w co-modeling, synthesis and verification techniques, that allow the majority of design work being done in the high level C domain. • An integrated high level design flow should seamlessly work or interface with the existing RTL design methodology and flow. • Thus, it includes the existing RTL flow such that it simplifies the execution of the existing RTL flow.