Amorphous silicon thin-film transistors for flexible electronics - PowerPoint PPT Presentation

Amorphous silicon thin-film transistors for flexible electronics Helena Gleskova, I-Chun Cheng, Ke Long, Sigurd Wagner, James Sturm Department of Electrical Engineering and Princeton Institute for the Science and Technology of Materials Princeton University Zhigang Suo Division of Engineering and Applied Sciences, Harvard University The work at Princeton University is supported by the United States Display Consortium. Berkeley, April 13, 2007

Flexible displays Lucent, E-Ink http://www.eink.com/iim/sale.html

Transistor “backplane” and display “frontplane” Amorphous silicon thin film transistor Schematic cross section generic backplane of a display Gate Source Drain Backplane | Frontplane Encapsulation Cr 1 μ m - 1 mm a-Si:H Display layer (LCD, PLED..) SiN x Passivation layer Transistor layer ~ 1 μ m Substrate Substrate: glass, steel, plastic 10 μ m - 1 mm Passivation layer • TFT backplane is generic for all flat panel technologies • Add display layer on top Gleskova H., Wagner S., IEEE Electron Device Letters 20 (1999), pp. 473-475.

Outline • Metal versus plastic foil substrate • a-Si:H TFT deposition temperature • Overlay alignment

Steel versus plastic Kattamis A.Z., Princeton University Cheng I-C. et al., IEEE EDL 27 (2006) 166. polymer foil substrate steel foil substrate up to ~1000°C < 280°C process temperature > 10 times higher low dimensional stability no some visually clear no yes permeable to O 2 or H 2 O rough moderate surface roughness yes some inert to chemicals yes no electrical conductor

Steel versus plastic Kattamis A.Z., Princeton University Cheng I-C. et al., IEEE EDL 27 (2006) 166. polymer foil substrate steel foil substrate process temperature up to ~1000°C < 280°C > 10 times higher low dimensional stability no some visually clear no yes permeable to O 2 or H 2 O rough moderate surface roughness yes some inert to chemicals yes no electrical conductor

a-Si:H TFTs made at 150ºC on Kapton Drain-to-source current I ds (A) V ds = 10 V Gate-to-source current I gs (A) T dep = 150ºC 10 -5 10 -5 0.1 V 10 -7 10 -7 Gate Source Drain I ds 10 -9 10 -9 I gs 10 -11 10 -11 10 -13 10 -13 -10 -5 0 5 10 15 20 Gate-to-source voltage V gs (V) I on /I off > 10 7 , μ lin ~ 0.45 cm 2 /Vs, V T ~ 2 V Acceptable TFT performance, but … Gleskova H. et al., J. Electrochem. Society 148 (2001), pp. G370-G374. Gleskova H. et al., J. Appl. Phys. 92 (2002), pp. 6224-6229.

Bias-stress instability of a-Si:H TFTs -4 10 Stress time: 600 sec -5 10 -6 10 Drain Current I D (A) -7 10 Initial -8 10 After stress of -9 10 V g = 20 V -10 10 -11 10 -12 10 -10 -5 0 5 10 15 20 Gate-to-Source Voltage V GS (V) Long K. et al., IEEE Electron Device Lett. 27 (2006), pp. 111-113.

a-Si TFT stability rises with process temperature Glass ( 300°C-350°C ) [2] Kapton-E ( 150°C ) [1] Threshold Change Δ V Τ (V) [1] Gleskova, IEEE TED, 10 2001 [2] Cheng, IEEE Proc. Glass ( 150°C ) [5] Solid-State and Integrated Circuit Tech., 1998 1 Glass ( 350°C ) [3] [3] Kanicki, APL, 1993 [4] Tsukada, JAP, 1991 Stress time: Glass ( 300°C-360°C ) [4] [5] Long, Princeton Univ. 600sec 0.1 10 7 V/m) Stress Field (*10 ⇒ Must make a-Si:H TFTs at high process temperature

a-Si:H TFTs made on clear plastic at 280ºC Cherenack K., Princeton University

a-Si:H TFT stability on clear plastic substrates Glass ( 300°C-350°C ) Kapton-E ( 150°C ) Threshold Change Δ V Τ (V) 10 Glass ( 150°C ) Clear plastic (150ºC) 1 Glass ( 350°C ) Glass ( 300°C-360°C ) Stress time: Clear Plastic (250ºC) 0.1 600sec 10 7 V/m) Stress Field (*10 Δ V T depends only on process T, not on substrate material Long K. et al., IEEE Electron Device Lett. 27 (2006), pp. 111-113.

Steel versus plastic Kattamis A.Z., Princeton University Cheng I-C. et al., IEEE EDL 27 (2006) 166. polymer foil substrate steel foil substrate up to ~1000°C < 280°C process temperature dimensional stability > 10 times higher low no some visually clear no yes permeable to O 2 or H 2 O rough moderate surface roughness yes some inert to chemicals yes no electrical conductor

Substrate stiffness affects dimensional stability thin film (small d f ) Y s ⋅ d s versus Y f ⋅ d f stiff (large Y f ) compliant (small Y f ) poly-Si TFT / steel substrate OLED / steel substrate Wu M. et al., APL 75 (1999) 2244 Wu C.C. et al., IEEE EDL 18 (1997) 609 stiff (large Y s ) thick Y s ⋅ d s >> Y f ⋅ d f Y s ⋅ d s >> Y f ⋅ d f substrate a-Si TFT / polymer substrate OTFT / polymer substrate (large d s ) Gleskova H., Princeton University Jackson T., Penn State Univ. compliant (small Y s ) Y s ⋅ d s ≈ Y f ⋅ d f Y s ⋅ d s >> Y f ⋅ d f

a-Si:H TFT process 1. Front SiN x passivation 2. Back SiN x passivation 80 nm 80 nm SiN x Kapton 500 nm 3. Cr gate metal deposition 4. Cr gate patterning - mask 1 Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

a-Si:H TFT process – cont. Cr (n + ) a-Si:H 80 nm undoped 50 nm a-Si:H 200 nm 300 nm SiN x Substrate 5. PECVD TFT stack: 5 W SiN x 5. PECVD TFT stack: 12 W SiN x (i) a-Si:H (i) a-Si:H (n + ) a-Si:H (n + ) a-Si:H 6. Cr S/D deposition 6. Cr S/D deposition 7. S/D patterning – mask 2 7. S/D patterning – mask 2 Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

Location of alignment marks 70 mm 52 mm 70 mm 2 1 52 mm feature of mask 1: roll axis 5 bottom gate metal layer 4 3 mask 1 & 2 40 μ m feature of mask 2: S/D layer Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

5W gate SiN x 2 1 ~ 52 mm shrinkage ~ 30 μ m 5 40 μ m 40 μ m shrink. ~ 20 μ m shrink. ~ 25 μ m ~ 52 mm ~ 52 mm 4 3 40 μ m shrinkage ~ 28 μ m ~ 52 mm 40 μ m 40 μ m Average shrinkage ~ 500 ppm Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

12W gate SiN x 2 1 ~ 52 mm stretching ~ 6 μ m 5 40 μ m 40 μ m 40 μ m 40 μ m shrink. ~ 1 μ m shrink. ~ 10 μ m ~ 52 mm ~ 52 mm 4 3 40 μ m 40 μ m stretching ~ 3 μ m ~ 52 mm 40 μ m 40 μ m 40 μ m 40 μ m Average change ~ 100 ppm Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

Film grown on foil substrate at elevated temperature α s (T d –T r ) Substrate at room temperature T r Substrate at deposition temperature T d ε s (T d ) ε bi < 0 Free-standing film at T d ε bi ε f (T d ) Workpiece at T d α s > α f after film growth α f (T d –T r ) Film and substrate at T r if they were separated ε f (T r ) Workpiece at T r when held flat ε s (T r ) [ ] ( ) ( ) α − α ⋅ − + ε T T f s r d bi ε = ν = ν ( ) T s r f s Y d + s s 1 Y d f f Gleskova H. et al., in Flexible Electronics: Materials and Applications, Gleskova H. et al., Appl. Phys. Lett. 88 (2006), 011905. Eds. Wong W.S., Salleo A., Springer-Verlag – to be published.

Film release from the substrate holder Workpiece at T r when held flat Workpiece at T r when released from the substrate holder SiN x R 24 Bare 8 19 40 mW/cm 2 2 ⎛ 2 ⎞ 2 Y d ⎛ + ⎞ ⎜ ⎟ Y d d f f f f f ⎜ ⎟ − + 1 4 1 ⎜ ⎟ ⎜ ⎟ 2 ⎜ ⎟ ⎝ ⎠ Y d d Y d s s s ⎝ ⎠ s s d = ⋅ s R [ ] ) ( ) ( ⎛ + ⎞ Y d d ( ) f f f + ν α − α ⋅ − + ε ⎜ ⎟ 6 1 1 T T ⎜ ⎟ f s r d bi Y d ⎝ ⎠ d s s s Cheng I-C. et al., J. SID 13 (2005), pp. 563-568. Suo Z. et al., Appl. Phys. Lett. 74 (1999), pp. 1177-1179.

Steel foil 0.1 60 T d 40 Curvature 1/R (cm -1 ) after film deposition 250 o C 0.05 Substrate strain 200 o C 20 ε s (T r ) (ppm) 150 o C Steel 0 0 -20 -0.05 compressive tensile -40 built-in stress built-in stress -0.1 -60 0.01 0.005 0 -0.005 -0.01 SiN x built-in strain A rigid substrate foil is not changed much by CTE mismatch Possible to maintain reasonable overlay accuracy Gleskova H. et al., in Flexible Electronics: Materials and Applications, Eds. Wong W.S., Salleo A., Springer-Verlag – to be published.

Kapton foil 1 1000 T d Curvature 1/R (cm -1 ) after film deposition 250 o C 0.5 500 Substrate strain 200 o C ε s (T r ) (ppm) 150 o C Kapton 0 0 -0.5 -500 compressive tensile built-in stress built-in stress -1 -1000 0.01 0.005 0 -0.005 -0.01 SiN x built-in strain Stress built into the SiN x can compensate thermal mismatch and eliminate curvature and misalignment Gleskova H. et al., in Flexible Electronics: Materials and Applications, Eds. Wong W.S., Salleo A., Springer-Verlag – to be published.

Summary • Higher deposition temperatures needed for good TFT stability • Deposition at elevated temperature changes in-plane dimensions d d f f • Changes are small if (steel) or (Kapton) < < 0 . 05 0 . 001 ~ ~ d d s s • CTE mismatch change in in-plane dimensions is ~ 20 ppm for a-Si:H TFTs on 100- μ m steel foil ~ 500 ppm for a-Si:H TFTs on 100- μ m Kapton foil • Tailor built-in stress in the film to compensate CTE mismatch ⇒ possible to eliminate misalignment ⇒ possible to eliminate curvature of the workpiece