Advanced Channel Engineering Achieving Aggressive Reduction of V T Variation for Ultra-Low-Power Applications K.Fujita, Y.Torii, M.Hori, J.Oh, L.Shifren*, P.Ranade*, M.Nakagawa, K.Okabe, T.Miyake, K.Ohkoshi, M.Kuramae, T.Mori, T.Tsuruta, S.Thompson*, T.Ema Fujitsu Semiconductor Ltd. *SuVolta Inc. 1
Outline • Introduction • Transistor Structure • Features of Process Flow and Verification • 65nm 6T-SRAM Evaluation Results • Summary 2
Introduction Power crisis V DD lowering Alternative V T variation solution RDF ETSOI, Tri-gate complicated 3
Transistor structure Deeply Depleted Channel TM (DDC) Transistor Depleted layer 1 V T setting offset layer 2 3 Screening layer Anti-punch-through layer 4 4
Process flow Well Implant V T / Screen Layer Implant 1 Blanket Si Epi-layer Formation STI Formation Gate Dielectric Formation for HV 2 Gate Dielectric Formation for LV Poly-Si Gate Formation Extension Implant (No Halo) 3 SW Formation S/D Formation 5
TEM of DDC transistor 43.1nm 6
Uniformity of epitaxial silicon Avg. = 27.2nm, 1sigma = 0.25% 7
TEM of low-temperature STI D S 8
W-dependence of V T 0.5 L=0.045 m NMOS 0.4 0.3 0.2 0.1 V T [V] 0 -0.1 -0.2 -0.3 -0.4 PMOS -0.5 0.1 1 10 Gate Width [ m] 9
I-V characteristics L=0.045 m |Vdd|=0.9, 0.1V 1E-02 PMOS NMOS 1E-03 1E-04 1E-05 I d [A/ m] 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 V g [V] 10
Summary of STI • Excellent STI profile • No anomalous W dependence • Nice sub-threshold characteristics No concern about low temp. STI 11
Breakdown of low-temperature GOX 3 L=0.045 m 2 S g =1E-7cm 2 1 0 LN(-LN(1-F)) -1 -2 -3 -4 -5 -6 -7 2 3 4 5 6 Breakdown Voltage [V] 12
NBTI of DDC PMOS 1E+10 T=125ºC 10 years 1E+09 L=0.045 m Lifetime@Id-10% [sec] 1E+08 1E+07 1E+06 1E+05 1E+04 1E+03 1E+02 1E+01 1E+00 1 10 2 3 4 5 Vstress [V] 13
HCI of DDC T=25ºC L=0.045 m 1E+10 PMOS NMOS 1E+09 Lifetime@Id-10% [sec] 1E+08 AC 10 years @ Duty 2% 1E+07 1E+06 1E+05 1E+04 1E+03 1E+02 1E+01 1E+00 -1 -0.5 0 0.5 1 1/V dd [1/V] 14
Summary of GOX • Excellent distribution of breakdown • Long enough life time for NBTI • Long enough life time for HCI No concern about low temp. GOX 15
V T distribution of NMOS 3 3 DDC DDC Cumulative Probability [ ] Cumulative Probability [ ] 2 2 1 1 0 0 -1 -1 -2 Baseline -2 Baseline -3 -3 0.2 0.4 0.6 0.8 0.2 0.4 0.6 0.8 Pull-down V T [V] Pass-gate V T [V] 16
V T distribution of PMOS 3 , Baseline Cumulative Probability [ ] , DDC 2 1 0 -1 -2 -3 -0.2 -0.4 -0.6 -0.8 Pull-up V T [V] 17
Summary of across-wafer variation 0.08 Baseline (pull-down) Baseline (pass-gate) Baseline (pull-up) V T across wafer [V] 0.06 DDC (pull-down) Baseline DDC (pass-gate) DDC (pull-up) 0.04 0.02 DDC 0.00 -0.8 -0.4 0 0.4 0.8 V T [V] 18
V T matching of NMOS 3 3 Baseline Baseline DDC DDC 2 2 Cumulative Probability [ ] Cumulative Probability [ ] 1 1 0 0 -1 -1 -2 -2 -3 -3 -0.2 -0.1 0 0.1 0.2 -0.2 -0.1 0 0.1 0.2 Pull-down V T [V] Pass-gate V T [V] 19
V T matching of PMOS 3 Baseline DDC 2 Cumulative Probability [ ] 1 0 -1 -2 -3 -0.2 -0.1 0 0.1 0.2 Pull-up V T [V] 20
Summary of V T matching 0.08 Baseline (pull-down) Baseline Baseline (pass-gate) Baseline (pull-up) V T / SQRT(2) [V] 0.06 DDC (pull-down) DDC (pass-gate) DDC (pull-up) 0.04 0.02 DDC 0.00 -0.8 -0.4 0 0.4 0.8 V T [V] 21
Butterfly curves of 6T-SRAM DDC Baseline 1.0 1.0 0.8 0.8 Node 2 [V] Node 2 [V] 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 Node 1 [V] Node 1 [V] 22
SNM distribution 3 Vdd=0.4V 2 Cumulative Probability [ ] 1 0 -1 -2 -3 Baseline -4 DDC -5 -100 0 100 200 SNM [mV] 23
V dd dependence of SNM 10 Baseline 9 DDC 8 SNM (mean/1 σ ) [ σ ] 7 6 5 4 3 2 1 0 0.0 0.2 0.4 0.6 0.8 1.0 V dd [V] 24
V ddmin of 576K bit SRAM array 100 Baseline Yield of SRAM macro [%] DDC 80 60 40 20 0 0.0 0.2 0.4 0.6 0.8 1.0 V dd [V] 25
Summary • Deeply Depleted Channel (DDC) transistor has been introduced to reduce RDF. • Process flow of DDC has been established. • V T matching of SRAM has been reduced to less than half by DDC. • Near to 0.4V operation of SRAM has been achieved. 26
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