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+ AB CD The switch model is attractive for manual calculations on - PowerPoint PPT Presentation

May 22, 2023 •247 likes •296 views

Digital IC Design Static CMOS V DD Chapter 6 p Pull-Up Net ll PUN PMOS Only l Combinational Logic Pull-Down Net PDN NMOS Only GND Continued Contin ed PUN and PDN are Dual Networks Example, Euler paths Propagation delay analysis

  1. Digital IC Design Static CMOS V DD Chapter 6 p Pull-Up Net ll PUN PMOS Only l Combinational Logic Pull-Down Net PDN NMOS Only GND Continued Contin ed PUN and PDN are Dual Networks Example, Euler paths Propagation delay analysis One strip for each + AB CD The switch model is attractive for manual calculations on path complex gates V DD V DD V DD DD Fix value on R eq is a reasonable approximation. D C Which value? An average value over different regions: A B Arrow end Arrow f + ABCD A B C D + B C R R start f = = = n V ( V ) n V ( V / 2) = + R OUT DD OUT DD ABCD eq n q - 2 2 A D ⎡ ⎤ ⎡ ⎤ V V + GND ⎢ DS ⎥ ⎢ DS ⎥ ⎣ ⎦ ⎣ ⎦ I I D = D = = ( V V ) ( V V /2) R OUT DD OUT DD eq n - 2 1

  2. 3V Example Analysis of Propagation Delay R eq-p ⎡ ⎤ ⎡ ⎤ V V + ⎢ DS ⎥ ⎢ DS ⎥ ⎣ I ⎦ ⎣ I ⎦ Three cases = = = D D ( V V ) ( V V / 2) R eq-p R eq-p R R OUT DD OUT DD q p q p − eq n 2 R eq-n A B 1. Pull up of one PMOS, Worst case t pLH = 0.69R p C L 3/200 μ = 15k Ω B C L 3/600 μ = 5k Ω -3 -2.5 -2 -1.5 -1 -0.5 0 2. Pull up of two PMOS at the same time 700 I D [uA] V DS 0 V GS =3 R eq-n t pLH = 0.69(R p / 2)C L 600 -50 500 1.5/180 μ 3. Pull down of NMOS 400 = 8.4k Ω -100 A 1.5/500 μ μ 300 300 t t pHL = 0.69(2R n )C L 0 69(2R )C = 3k Ω -150 200 R eq-n 100 -200 0 V DS V GS =-3 I D [uA] 0 0.5 1 1.5 2 2.5 3 -250 R eq-p = (15+ 8.4)/ 2 = 11.7k Ω R eq-n = (3+ 5)/ 2 = 4k Ω NAND See also equation 3.43 Scale Factor Scale Factor for Worst Case Long Channel Assuming L 1 W p ≈ 3 W n ∝ ∝ R proportional to one over the width: R W W 1 1 3 3 2 * 3 = 6 A B A B A A 2 * 3 = 6 B C L B C L For stacked (series) transistors, 2 = + 2 * 1 = 2 B L L L total length is double tot A B B A A A B C L 2 2 * 1 = 2 1 1 Lower hole mobility, in PMOS gives ' ≈ ' ≈ K K ' K K ' NAND NAND NAND NAND NOR NOR n (Long Channel) n (Short Channel) 3 3 . 5 K ' K ' Factor for For stacked For stacked p p stacked and low hole and low hole Never change the length (except for pseudo-NMOS) transistors mobility mobility Choose the one with lowest total width = smaller area and C (3.5 for short channel) 2

  3. Problem 2 Problem 2 - Soultion W/L = 2/0.35 k n ’/k p ’ = 3 V a) Dimension worst case to DD A B C E be as balanced inverter. D F X A b) Express lowest resistance D B in terms of total resistance, R , if X = 1 C F E 3

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