A Survey of Satisfiability Modulo Theory (for mathematicians) David - PowerPoint PPT Presentation

A Survey of Satisfiability Modulo Theory (for mathematicians) David Monniaux VERIMAG GNCS, Pescara, February 10, 2017 David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 1 / 48 STATOR

SMT = SAT + theories SAT = say whether a formula over Booleans is satisfiable (and give a model if so) satisfiable (and give a model if so) Here theory = linear real arithmetic (LRA) or linear integer arithmetic (LIA) David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 2 / 48 SMT = say whether a formula over Booleans and other types is ( x ≤ 0 ∨ x + y ≤ 0 ) ∧ y ≥ 1 ∧ x ≥ 1 unsatisfiable for x , y ∈ R ( x ≤ 0 ∨ x + y ≤ 0 ) ∧ y ≥ 1 satisfiable for x , y ∈ Z STATOR

DPLL and CDCL Contents DPLL and CDCL DPLL(T) Natural domain SMT Exponential behaviour of DPLL(T) Abstract CDCL (ACDCL) Model-construction satisfiability calculus (MCSAT) Other topics Conclusion David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 3 / 48 STATOR

4 / 48 David Monniaux (VERIMAG) Propositional satisfiability (SAT) (possibly “if then else”, “exclusive-or” etc.) DPLL and CDCL 2017-02-10 A Survey of Satisfiability Modulo Theory Output: “unsat” or a model (satisfying assignment) Input: formula with ∧ , ∨ ( a ∧ ¯ c ) ∨ ( b ∧ c ∧ ¯ ∧ (¯ ( ) b ∧ ¯ d ) b ∨ ¯ c ) . STATOR

DPLL and CDCL Conjonction normal form (CNF) View the SAT formula as a system of constraints a ) convert from arbitrary formula to CNF cannot be done efgiciently keeping only original variables (exponential blowup, per distributivity) David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 5 / 48 = clauses (disjunctions of literals a or ¯ ( a ∨ b ) ∧ ( c ∨ d ) − → ( a ∧ c ) ∨ ( a ∧ d ) ∨ ( b ∧ c ) ∨ ( b ∧ d ) STATOR

6 / 48 c d A Survey of Satisfiability Modulo Theory c 2017-02-10 DPLL and CDCL Assign propositional variables to sub-formulas: David Monniaux (VERIMAG) Add extra variables Tseitin encoding ( a ∧ ¯ c ) ∨ ( b ∧ c ∧ ¯ ∧ (¯ ( ) b ∧ ¯ d ) b ∨ ¯ c ) . e ≡ a ∧ ¯ f ≡ b ∧ c ∧ ¯ b ∧ ¯ g ≡ e ∨ f h ≡ ¯ b ∨ ¯ ϕ ≡ g ∧ h ; STATOR

7 / 48 c DPLL and CDCL A Survey of Satisfiability Modulo Theory 2017-02-10 c b c turned into clauses David Monniaux (VERIMAG) Tseitin encoding d c e ≡ a ∧ ¯ f ≡ b ∧ c ∧ ¯ b ∧ ¯ g ≡ e ∨ f h ≡ ¯ b ∨ ¯ ϕ ≡ g ∧ h ; e ∨ ¯ ¯ e ∨ a ¯ ¯ e ∨ ¯ ¯ a ∨ b ∨ c ∨ e ¯ ¯ ¯ ¯ b ∨ ¯ f ∨ b f ∨ c f ∨ d c ∨ d ∨ f ¯ ¯ ¯ e ∨ g f ∨ g g ∨ e ∨ f ¯ h ∨ ¯ b ∨ h c ∨ h b ∨ ¯ ¯ ¯ g ∨ ¯ ¯ ϕ ∨ g ϕ ∨ h h ∨ ϕ ϕ STATOR

DPLL and CDCL DPLL Each clause acts as propagator e.g. Boolean constraint propagation aka unit propagation : propagate as much as possible once the value of a variable is known, use it elsewhere David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 8 / 48 assuming a and ¯ b , clause ¯ a ∨ b ∨ c yields c STATOR

DPLL and CDCL DPLL: Branching If unit propagation insufgicient to Then: David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 9 / 48 ▶ either find a satisfying assignment ▶ either find an unsatisfiable clause (all literals forced to false) ▶ pick a variable ▶ do a search subtree for both polarities of the variable STATOR

10 / 48 c David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 DPLL and CDCL c Now g and h are t , c b Example e ∨ ¯ ¯ ¯ ¯ e ∨ ¯ ¯ e ∨ a a ∨ b ∨ c ∨ e ¯ ¯ ¯ ¯ f ∨ b f ∨ c f ∨ d b ∨ ¯ c ∨ d ∨ f ¯ ¯ ¯ e ∨ g f ∨ g g ∨ e ∨ f ¯ h ∨ ¯ b ∨ ¯ b ∨ h c ∨ h ¯ ¯ g ∨ ¯ ¯ ϕ ∨ g ϕ ∨ h h ∨ ϕ ϕ From unit clause ϕ ¯ ¯ g ∨ ¯ ¯ ϕ ∨ g → g ϕ ∨ h → h h ∨ ϕ removed ¯ ¯ e ∨ g removed f ∨ g removed b ∨ h removed ¯ h ∨ ¯ c → ¯ ¯ c ∨ h removed g ∨ e ∨ f → e ∨ f b ∨ ¯ b ∨ ¯ STATOR

11 / 48 DPLL and CDCL Add this clause (maybe garbage-collected later) to H d A Survey of Satisfiability Modulo Theory 2017-02-10 Learn clause = negation of bad hypotheses, implies by H : Used by unit propagation David Monniaux (VERIMAG) Trace back to a subset of hypotheses, sufgicient for contradiction. Both t and f inferred from hypotheses H by unit propagation. both t and f . A DPLL branch gets closed by contradiction : a literal gets forced to CDCL: clause learning e.g. a ∧ ¯ b ∧ ¯ c ∧ d ∧ H = ⇒ f a ∨ b ∨ c ∨ ¯ ¯ STATOR

DPLL and CDCL Proof systems CDCL DAG resolution (shared proof subtrees) = linear resolution tree resolution. (Independent of search strategy.) David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 12 / 48 DPLL Tree resolution Some problems have exponentially smaller proofs in DAG than STATOR

DPLL and CDCL Implementation wise Clause simplification etc. implemented as two watched literals per clause Pointers to clauses used for deduction Highly optimized proof engines Preprocessing David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 13 / 48 ▶ Minisat ▶ Glucose STATOR

DPLL(T) Contents DPLL and CDCL DPLL(T) Natural domain SMT Exponential behaviour of DPLL(T) Abstract CDCL (ACDCL) Model-construction satisfiability calculus (MCSAT) Other topics Conclusion David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 14 / 48 STATOR

15 / 48 DPLL(T) 2017-02-10 A Survey of Satisfiability Modulo Theory David Monniaux (VERIMAG) d . d DPLL(T) (Improper terminology, should be CDCL(T)) ( x ≤ 0 ∨ x + y ≤ 0 ) ∧ y ≥ 1 ∧ x ≥ 1 ↓ dictionary of theory literals ( a ∨ b ) ∧ c ∧ d Solve, get ( a , b , c , d ) = ( t , f , t , t ) . But x ≤ 0 ∧ x ≥ 1 is a contradiction! a ∨ ¯ Add theory lemma ¯ Solve, get ( a , b , c , d ) = ( f , t , t , t ) . But x + y ≤ 0 ∧ ≥ 1 ∧ x ≥ 1 is a contradiction! Add theory lemma ¯ c ∨ ¯ b ∨ ¯ The problem is unsatisfiable . STATOR

DPLL(T) DPLL(T) In practice, do not wait for the CDCL solver to provide a full assignment. Check partial assignments for theory feasibility. If during theory processing, a literal becomes known to be t or f , propagate it to CDCL. Boolean relaxation of the original problem. Lazy expansion of theory. David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 16 / 48 e.g. x ≥ 0, x ≥ 1 assigned, propagate x + y ≥ 0 STATOR

DPLL(T) Linear real arithmetic Usually decided by exact precision simplex . Extract from the tableau the contradictory subset of assignments. David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 17 / 48 STATOR

18 / 48 2 LRA Example 2017-02-10 A Survey of Satisfiability Modulo Theory David Monniaux (VERIMAG) (1) 20 DPLL(T)  ≤ 2 x + y   − 6 ≤ 2 x − 3 y    − 1000 ≤ 2 x + 3 y ≤ 18 ≤ − 2 x + 5 y − 2     ≤ x + y .  STATOR

19 / 48 20 2 x 2 2 x 2 x 3 y DPLL(T) x (2) David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 LRA Example  a = + y ≤ a   b = − 3 y − 6 ≤ b    c = − 1000 ≤ c ≤ 18 d = + 5 y − 2 x − 2 ≤ d     e = + y ≤ e .  STATOR

20 / 48 LRA Example Gauss-like pivoting until: 2017-02-10 A Survey of Satisfiability Modulo Theory David Monniaux (VERIMAG) (3) DPLL(T)  e = 7 / 16 c − 1 / 16 d   a = 3 / 4 c − 1 / 4 d    b = 1 / 4 c − 3 / 4 d x = 5 / 16 c − 3 / 16 d     y = 1 / 8 c + 1 / 8 d .  STATOR

21 / 48 12 0 0 20 David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory x 1 2017-02-10 DPLL(T) (4) Relevant original inequalities can be combined into an unsatisfiable one (thus the theory lemma ) LRA Example e = 7 / 16 c − 1 / 16 d But: c ≤ 18 and d ≥ − 2, so − 7 / 16 c − 1 / 16 d ≤ 8. But we have e ≥ 20, thus no solution . 7 / 16 ( − 2 x − 3 y ) ≥ − 7 / 16 × 18 1 / 16 ( − 2 x + 5 y ) − 1 / 16 ≥ × 2 + y ≥ ≥ STATOR

DPLL(T) Linear integer arithmetic Linear real arithmetic + David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 22 / 48 ▶ branching: if LRA model x = 4 . 3, then x ≤ 4 ∨ x ≥ 5 ▶ (sometimes) Gomory cuts STATOR

DPLL(T) Uninterpreted functions David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 23 / 48 f ( x ) ̸ = f ( y ) ∧ x = z + 1 ∧ z = y − 1 ↓ f x ̸ = f y ∧ x = z + 1 ∧ z = y − 1 Get ( x , y , z , f x , f y ) = ( 1 , 1 , 0 , 0 , 1 ) . But if x = y then f x = f y ! Add x = y = ⇒ f x = f y . The problem over ( x , y , z , f x , f y ) becomes unsatisfiable . STATOR

DPLL(T) Arrays David Monniaux (VERIMAG) A Survey of Satisfiability Modulo Theory 2017-02-10 24 / 48 update ( f , x 0 , y 0 ) the function mapping ▶ x ̸ = x 0 to f [ x ] ▶ x 0 to y 0 . STATOR

25 / 48 David Monniaux (VERIMAG) Qvantifiers Show this formula is true: DPLL(T) (5) Equivalently, unsatisfiable: 2017-02-10 A Survey of Satisfiability Modulo Theory ( ∀ i 0 ≤ i < j = ⇒ t [ i ] = 42 ) = ⇒ ( ∀ i 0 ≤ i ≤ j = ⇒ update ( t , j , 0 )[ i ] = 42 ) 0 ≤ i 0 ≤ j ∧ update ( t , j , 0 )[ i 0 ] = 0 ∧ ( ∀ i 0 ≤ i < j = ⇒ t [ i ] = 0 ) STATOR