A Sum Error Detection Scheme for Decimal Arithmetic www.itmati.com Alvaro Vázquez ITMATI. Technological Institute for Industrial Mathematics (Spain) and Elisardo Antelo University of Santiago de Compostela (Spain) ARITH24 Conference
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Summary 1 Introduction 2 BCD sum checker 3 Mixed binary/BCD sum checker 4 Sign-magnitude sum checker 5 Evaluation and Comparison 6 Conclusion ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Summary 1 Introduction 2 BCD sum checker 3 Mixed binary/BCD sum checker 4 Sign-magnitude sum checker 5 Evaluation and Comparison 6 Conclusion ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Objectives of this work Concurrent error detection for both binary and BCD addition/subtraction. Fully protection against single faults or event upsets (soft errors). Avoid hardware duplication. Avoid adder redesign. 1/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Sum checkers for concurrent error detection 1. Self-checking adders. ⊲ Require adder redesign. ⊲ Based on a variety of techniques: - Parity prediction. - Residue codes. - Berger code prediction. - Double-rail checking of carries. 2. Separable: ⊲ Avoid adder redesign. ⊲ Only two different proposal: - Unit duplication (sheer redundancy). - Carry-save checkers. 2/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Unit duplication X Y Main Adder Replicated Adder k z k−1 z n−1 z s s 0 z s s k k−1 n−1 0 Z S Error Checker OR TREE err err (a) General layout. (b) Error checker (comparator). Figure: Sum checking using unit replication. 3/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Carry-save checkers for binary addition (I) Previous work: Separable carry-free error detection mechanisms for fast, unpipelined binary integer/fixed-point addition: ⊲ Used to check A + B = K without carry propagation (Cortadella et al, 1992). ⊲ Lazy adder checker: carry-save checker with custom full-adder (Yilmaz et al, 2007). ⊲ Long residue checker: carry-save checker with standard cell full-adders (Sullivan et al, 2012). Separable error detectors for pipelined mixed parallel prefix and carry-ripple adders (Sullivan et al, 2013). 4/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Carry-save checkers for binary addition (II) X Y Adder S Carry−free Adder CV SV Error Checker err Figure: General block diagram. 5/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Carry-save checkers for binary addition (III) x y s k k k s x y k k k Full Adder 1 0 Mux−2 cv cv k k sv cv sv cv k k−1 k k−1 (a) Lazy Adder Checker (b) Long Residue Checker = p k ⊕ s k = p k ⊕ p k ⊕ c k = c k sv k = p k y k ∨ p k s k = p k y k ∨ p k s k = c k + 1 cv k = x k ⊕ y k ⊕ s k = p k ⊕ p k ⊕ c k = c k sv k = x k y k ∨ ( x k ∨ y k ) s k = x k y k ∨ p k c k = c k + 1 cv k 6/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion New contributions of this work Algorithm and architecture of separable carry-save (CS) checker for the following operations/number systems: 1. 10’s complement BCD add/sub. 2. Mixed 2’s complement binary/10’s complement add/sub 3. BCD sign-magnitude add/sub ⇒ Extension to mixed binary/BCD SM straightforward Simple conditions for error detection in terms of word-length operands X , Y and S ⇒ Fused into single condition by recoding to radix-16. Decimal CS addition implemented using binary radix-16 + simple combinational logic for decimal correction ⇒ Easy integration into the binary CS checker. 7/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Summary 1 Introduction 2 BCD sum checker 3 Mixed binary/BCD sum checker 4 Sign-magnitude sum checker 5 Evaluation and Comparison 6 Conclusion ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Word-length operand condition for add/sub checking (I) Binary 2’s complement 1. Addition: X + Y = S ⇒ X + Y − S = 0 X + Y + S + 1 = 2 n − 1 ⇒ 2. Subtraction: X − Y = S ⇒ X − Y − S = 0 X + Y + S + 1 = 2 n − 1 ⇒ 3. Add/Sub: n − 1 n / 4 − 1 X + Y B + S + sub = 2 k = ( 15 ) 16 i ⇔ � n ∑ ∑ k = 0 ( sv k ⊕ hv k ) = 0 k = 0 i = 0 � IF ( sub == 0 ) Y Y B = Y ELSE 8/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Word-length operand condition for add/sub checking (II) BCD 10’s complement 1. Addition: p − 1 ∑ ( 15 ) 10 i X + Y = S ⇒ X + Y − S = 0 ⇒ X + Y + S = i = 0 p − 1 with − S = S − ∑ i = 0 ( 15 ) 10 i . 2. Subtraction: X − Y = S ⇒ X − Y − S = 0 ⇒ p − 1 p − 1 ( 15 ) 10 i = ∑ ∑ ( 15 ) 10 i ⇒ X + Y + S − i = 0 i = 0 3. Add/Sub: p − 1 X + Y D + S + sub ? ∑ ( 15 ) 10 i = i = 0 � IF ( sub == 0 ) Y Y D = Y + 6 ELSE 9/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Binary radix-16 approximation of BCD Carry-save (I) ? ? | X i + Y D = 15 ⇒ | X i + Y B i + S B i + S i + C i | 10 i + C i | 16 = 15 C i + 1 = G i ∨ A i C i � IF ( X i + Y A i ≥ 16 ) 1 G i = 0 ELSE � IF ( X i + Y A i ≥ 15 ) 1 A i = 0 ELSE Y A i = Y D i + 6 10/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Proposed architecture for BCD add/sub checking X Y S X Y i i 4 sub 4 Digitwise decimal corrections I Conditional bit inversion B Y B S Digitwise +6 if sub=0 sub Bit inversion if sub=1 A Y 3:2 Carry−save adder i CV 4 1−bit left shift HV SV Carry−prefix tree Error Checker A i (4 bits) Digitwise −6 if Ai=0 G 4 i B Y I i err i (c) General layout. (d) Decimal correction block. s s s s i,1 i,3 i,2 i,0 I i B B B s B s s s i,1 i,0 i,3 i,2 (e) Sum inversion block. 11/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Binary radix-16 approximation of BCD Carry-save (II) � Y i − 6 IF ( sub == 0 ) Y A i = Y i ELSE � Y A i − 6 IF ( A i == 0 ) Y B i = Y A ELSE i � S i − 6 IF ( I i == 1 , S i == 9 ) S B i = S i ELSE I i = A i G i 12/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Fault secure checker There might be a case that an induced error in S i could be not detected when I i = A i G i == 1 ⇔ X i + Y D i == 9 by using S ∗ i + C ∗ i = X i + Y D i Only two possible values of S i could not be detected as errors when I i == 1: S i = 0 when C ∗ i == 1 S i = 9 when C ∗ i == 0. But we discard S i = 0 by construction. It could be possible that when I i == 1, still an error of 9 is not detected due to an error in C ∗ i Such an error would be detected always in the least significant bit, since C 0 = sub is a preasigned value. 13/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Summary 1 Introduction 2 BCD sum checker 3 Mixed binary/BCD sum checker 4 Sign-magnitude sum checker 5 Evaluation and Comparison 6 Conclusion ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Architecture Mixed Bin/BCD Checker Y X i i 4 4 Digitwise +6 if sub=0 dec and dec=1 sub Bit inversion if sub=1 A Y i Carry−prefix computation 4 (4 bits) G A i i Digitwise −6 if Ai=0 and dec=1 I dec dec i 4 B Y i Figure: Decimal correction block for the bin/dec sum error checker. Y B i = Y A i − 6 · ( A i dec ) IF ( sub == 0 , dec == 0 ) Y i Y A i = ELSEIF ( sub == 1 ) Y i Y i + 6 ELSE 14/ 23 ARITH24
Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion Summary 1 Introduction 2 BCD sum checker 3 Mixed binary/BCD sum checker 4 Sign-magnitude sum checker 5 Evaluation and Comparison 6 Conclusion ARITH24
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