A Model-based Embedded Control Hardware/Software Co-design Approach for Optimized Sensor Selection of Industrial Systems Kyriakos M. Deliparaschos, Konstantinos Michail, Spyros G. Tzafestas, Argyrios C. Zolotas 23rd Mediterranean Conference on Control and Automation (MED 2015) Torremolinos – SPAIN, 16 – 19 June 2015
Contents Introduction and proposed framework • Electromagnetic suspension (EMS) test case • FIL and FPGA architecture of LQG controller • Results • Conclusions • 2
Hardware-in-the-loop (HIL) • HIL widely used in developing/testing complex real-time control systems • Simulation model of the plant is part of the test platform • Model-based embedded control hw/sw co-design approach is followed Physical process FPGA Software-based Communication protocol Hardware-based • System is realized in soft form, i.e., plant model (Ethernet link) controller using a high-level language (e.g., MATLAB/Simulink) • In embedded control system: the model of the plant (realized on sw) interfaces with the actual controller (implemented on hw) via a communication link 3
System-level design • Control design Disturbances • Maintain performance Uncertainties in an integrated framework System • Even if sensors/ Non-linearities Inherently actuators given, which Faults Faults Unstable may be the “better” set for the above? 4
Electromagnetic suspension test case EMS serves two • purposes: Controller Track K Flux circulation Supports the Pole • Airgap vehicle and Electromagnet Driving passengers Signal Current F Vert. Accleration Power Amplifier Vert. Velocity Mg Suspended mass Ensures proper ride (m) • quality 5
Input excitations and performance specs Deterministic − Table 1 MAGLEV suspension constraints Constraints Value RMS acceleration ( rms & z & ) < 0.5ms -2 z − RMS gap variation, (( z ) ) < 5mm t rms Control effort, ( rms u ) < 300V(3I o R o ) Stochastic z − Air gap deviation, (( z ) ) < 7.5mm t p Control effort, (u p ) < 300V(3I o R o ) Settling time, (t s ) < 3s Steady state error ( e ) =0 ss cles, & & - aiming for minimal set of sensors φ = φ = & & Performance specs Test inputs 6 − − = + + ω & = + ω η <
Design procedure • Overall control constraint Initialise Algorithm violation function Select first Sensor set Optimize closed-loop • If Ω =0 then performance performance by using Genetic Algorithms requirements are satisfied. If Yes Ω≠ 0 then there is some Select the ‘‘best’’ controller violation of control constraints More sensor sets? • Controller selection criteria No Select the best sensor set for final selection of controller 7
Optimized sensor selection for the EMS LQR LQR full state With LQG Test Similar response maintaining performance 8
FPGA-in-the-loop (FIL) framework for optimized sensor selection • FPGA-targetted HIL technique -> FPGA-in- Optimised sensor selection the-loop (FIL) Physical Process (Non-linear MAGLEV suspension model) • FIL schematic for EMS Network fabric + - + + + + • Out of all available + + + outputs, y f , feed the LQR KBE best sensor set y o into Software model (MAGLEV) Hardware model (LQG Controller) the FIL-based LQG. 9
LQG design architecture Sensor measurements • A detailed LQG core K*u model using explicitly K*u Control input scalar buses K*u Estimated states • 3 sensor measurements current gain K*u (y 1 , y 2 , y 3 ) velocity gain K*u airgap gain K*u fixpt scaling K*u (a) 10
Hardware Description Language (HDL) code generation • LQG conversion from floating-point 1 LIBRARY IEEE ; USE IEEE . std_logic_1164 . ALL ; 2 domain to fixed-point domain 3 USE IEEE . numeric_std . ALL ; 4 5 ENTITY LQG IS 6 PORT ( clk : IN std_logic ; 7 r s t : IN std_logic ; 8 clk_en : IN std_logic ; • MathWorks HDL Coder tool used to 9 c o n t r o l _ i n : IN std_logic_vector (25 DOWNTO 0) ; − − sfix26_En19 10 i _ i n p u t _ i n : IN std_logic_vector (31 DOWNTO 0) ; − − sfix32_En28 11 b_in : IN std_logic_vector (31 DOWNTO 0) ; − − sfix32_En35 automate and speed up the process 12 a_in : IN std_logic_vector (31 DOWNTO 0) ; − − sfix32_En31 13 ce_out : OUT std_logic ; of translating high level simulation 14 uc_d_op : OUT std_logic_vector (34 DOWNTO 0) ; − − sfix35_En27 15 i_op : OUT std_logic_vector (35 DOWNTO 0) ; − − sfix36_En24 16 z_dot_op : OUT std_logic_vector (35 DOWNTO 0) ; − − sfix36_En23 model into equivalent Register 17 gap_op : OUT std_logic_vector (34 DOWNTO 0) ; − − sfix35_En23 18 igap_op : OUT std_logic_vector (35 DOWNTO 0) − sfix36_En23 − Transfer Level (RTL) HDL description 19 ) ; 20 END LQG; (i.e., VHDL) In1 In2 In3 • HDL Coder limitations in handling multi dimension matrices, hence: A(2,1) A(1,2) A(2,2) A(3,2) A(2,3) A(1,1) A(3,1) A(1,3) A(3,3) Detailed LQG core model using explicitly scalar buses was developed prior to HDL translation 3x3 sub-block) Out1 Out2 Out3 (i.e., architecture of A (b) 11
HW/SW co-design FPGA flow • Top-down method: for the design • Co-simulation of RTL model and fixed-point Simulink model using process of the LQG controller MathWorks HDL Verifier and Mentor Modelsim simulator • Model specifications and system requirements -> high level • Compare system implemented on functional system model -> FPGA chip (in real time) using a conversion to fixed-point cycle accurate Simulink model (pre- FPGA implementation) forming a FIL setup Algorithmic Model analysis and Testbench specifications implementation in Discretization floating point MATLAB Diff Algorithm + - Model conversion Quantization in Stimuli Results fixed point RTL design Co-simulation with Integration with Implementation MATLAB HDL Simulator peripheral cores in Implementation on (Ethernet MAC, FPGA RTL VHDL DCM) FPGA Testbench Logic Diff 12 synthesis Algorithm + - Stimuli Results ML605 FPGA Board Ethernet Place FPGA device link and configuration Route FPGA-in-the-Loop simulation
Design utilization results • FPGA design utilization Module ( iba ) Slices Slice Reg. LUTs DSP48E1 LQG 0/265 0/113 0/884 0/73 KBE 49/221 77/77 170/717 1/50 Summary for the LQG A d 67/67 0/0 221/221 27/27 C d 30/30 0/0 99/99 14/14 K d controller with current/flux/ 75/75 0/0 227/227 8/8 lqg LQR 44/44 36/36 167/167 23/23 Module ( b ) Slices Slice Reg. LUTs DSP48E1 accel and flux modules LQG 0/205 0/111 0/696 0/69 KBE 41/161 75/75 143/529 1/46 A d 69/69 0/0 220/220 27/27 C d 12/12 0/0 30/30 6/6 K d 39/39 0/0 136/136 12/12 lqg • FIL implemented on a Xilinx LQR 44/44 36/36 167/167 23/23 Slices Slice Registers Virtex-6 ML605 development 0.04 0.74 0.04 0.8 0.04 D of available 0.54 D of available board utilizing a Xilinx 0.03 0.6 0.03 0.02 0.4 0.02 Virtex-6 device 0.01 0.01 0.21 0.19 0.17 0.13 0.12 0.12 0.12 0.12 0.2 0.09 0.01 0.02 0.00 0.00 0.00 0.00 0.00 0.00 (XC6VLX240T-1FFG1156) 0 0 LQG KBE LQR LQG KBE LQR LUTs DSP48E1 0.8 12 9.51 0.59 8.98 10 • LQG and the peripheral cores 0.6 D of available 0.47 D of available 8 0.4 6 synthesized via Xilinx 3.52 3.52 2.99 2.99 4 0.15 0.15 0.15 0.11 0.11 0.11 1.82 0.2 0.10 0.09 1.56 0.07 1.04 0.78 2 0.02 Synthesis Tool (XST) 0.13 0.13 0 0 LQG KBE LQR LQG KBE LQR 13
Design speed achievement* 29.1MHz clock operating freq (current/flux/accel) • 30.5MHz clock operating freq (flux) • Map and place and route effort was set to medium • *according to post-place and route timing report on Xilinx ISE 13.3 14
EMS performance − 4 x 10 6 4 2 0 • Airgap error with flux 0 1 2 3 4 5 6 − 4 x 10 6 and current/flux/accel 4 2 0 0 1 2 3 4 5 6 • State estimation with Current with LQR 4 Estimated current with FIL 2 flux (deterministic input) 0 0 1 2 3 4 5 6 0.6 Velocity with LQR Estimated velocity with FIL 0.4 • Continuous-time vs. FIL 0.2 0 0 1 2 3 4 5 6 (discrete/quantized) − 3 x 10 6 Airgap with LQR 4 Estimated airgap with FIL 2 0 0 1 2 3 4 5 6 15
Conclusions Embedded control system for EMS sensor optimization via FIL • Matlab/Simulink hosts the physical process and LQG • implemented on FPGA The design approach followed a fusion of system modeling and • hw/sw co-design Economical FPGA implementation due to early quantization • analysis in the design process Results on two sensor set examples and illustration of FIL • advances in accelerating system validation 16
A Model-based Embedded Control Hardware/Software Co-design Approach for Optimized Sensor Selection of Industrial Systems Kyriakos M. Deliparaschos, Konstantinos Michail, Spyros G. Tzafestas, Argyrios C. Zolotas 23rd Mediterranean Conference on Control and Automation (MED 2015) Torremolinos – SPAIN, 16 – 19 June 2015
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