A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load Presented by Tan Xiao Liang Supervisor: A/P Chan Pak Kwong School of Electrical and Electronic Engineering 1
Outline • Introduction of LDO Regulator • Multi-gain Stages in Output Capacitorless (OCL-LDO) regulator • Negative Current Feedback (NCF) Technique • Weighted Current Feedback (WCF) Technique • Circuit Implementation of WCF LDO regulator • Results and Discussions • Conclusion
Introduction of LDO regulator • Widely used due to its simple structure, fast response and low noise characteristics. • Output capacitorless LDO (OCL-LDO) regulator eliminates the large output capacitor and support fully on- chip applications. • For large scale digital circuits, the effective supply line parasitic capacitance is large. The regulator needs to drive a wide range of load capacitance (C L ) with fast transient response.
Multi-gain Stages in a LDO Regulator Frequency Compensation N 1 (V 1 ) N 2 (V 2 ) N P (V P ) N O (V OUT ) V REF p -3dB p 2 p 3 p O M P 1 st stage 2 nd stage 3 rd stage -g mp g m1 -g m2 -g m3 R O R 1 R 2 R P C L ≈ 1/g m C P C 1 C 2 Power T. Feedback Network 1. N 2 is low impedance node and N P is high impedance node. 2. p 3 and p O are low, limiting the stability at light I L . 3. Speed at node N P is small due to limited quiescent bias current in 3 rd stage.
Negative Current Feedback Technique Frequency Compensation N 1 (V 1 ) N 2 (V 2 ) N P (V P ) N O (V OUT ) V REF p -3dB p 2f p 3 p O M P 2 nd stage 3 rd stage 1 st stage -g mp -g m2 -g m3 g m1 R 1 R 2 R O R P C 1 C 2 Power T. C L C P NCF Loop R P ≈ (1/g m ) g mf V P Current Sensor (+g mf ) Feedback Network 1. N P is low impedance node and N 2 is high impedance node. 2. 3 rd stage is adaptively biased leading to a high speed. 3. Large R 2 and large C P results in two low frequency parasitic poles. 4. Negative feedback technique to reduce R 2 .
Negative Current Feedback Technique Frequency Compensation N 1 (V 1 ) N 2 (V 2 ) N P (V P ) N O (V OUT ) V REF p -3dB p 2f p 3 p O M P 2 nd stage 3 rd stage 1 st stage -g mp -g m2 -g m3 g m1 R 1 R 2 R O R P C 1 C 2 C L Power T. C P NCF Loop R P ≈ (1/g m ) g mf V P Current Sensor (+g mf ) Feedback Network 1. Negative feedback current reduce R 2 thus reduce the loop gain of the regulator as well. The regulation accuracy is degraded. 2. The charging/discharging rate at node N 2 is also reduced.
Weighted Current Feedback Technique: Operation Frequency Compensation WCF (+g mf ) V REF N O N 1 N 2 N P (V OUT ) (V 1 ) (V 2 ) (V P ) 1 st stage 2 nd stage 3 rd stage N P Power T. +g m1 -g m2 -g m3 M P (-g mp ) C L V DD 2 nd stage 3 rd stage R L S B N 1 N P R X M 2 Overshoot M d1 M a1 M a2 Reduction R P R 2 I a1 I a2 WCF N 2 Loop M 3 M a3 V B Weighted Current M b1 M a5 M a4 Feedback (WCF) v fbin v fbout
Weighted Current Feedback Technique: Operation V DD V DD V DD S S S N 1 B N 1 B N 1 B R X R X R X M 2 M 2 M 2 M d1 M a1 M a2 M d1 M a1 M a2 M d1 M a1 M a2 I a1 I a1 I a1 I a2 I a2 I a2 N 2 N 2 N 2 M 3 M 3 M 3 M a3 M a3 M a3 V B V B V B M b1 M a5 M a4 M b1 M a5 M a4 M b1 M a5 M a4 WCF WCF WCF (a) (b) (c) 1. At low I L , both M a1 and M a2 are weakly biased. Feedback is small. 2. At moderate I L , both M a1 and M a2 are in saturation region. Feedback is strong. 3. At high I L , M a2 is forced to work in linear region by M a3 and M a4 . Feedback is reduced.
Weighted Current Feedback Technique: Why it works? Frequency Compensation N 1 (V 1 ) N 2 (V 2 ) N P (V P ) N O (V OUT ) V REF p -3dB p 2f p 3 p O M P 2 nd stage 3 rd stage 1 st stage -g mp -g m2 -g m3 g m1 R O R 1 R 2 R P C 1 C 2 C L Power T. C P WCF Loop R P ≈ (1/g m ) g mf V P Current Sensor (+g mf ) Feedback Network • At low I L , R O is large, C L R O forms the dominant pole. ω UGF is small. Feedback can be small to achieve stability. • At moderate I L , loop gain is large. R 2 and R P are moderate. A strong feedback is required to reduce R 2 and the loop gain. • At high I L , R P is small. R 2 is also small due to a large bias current introduced by the WCF circuit. The feedback can be reduced.
WCF loaded Output Impedance & Feedback Factor 1. R 2f (feedback loaded impedance at node N 2 ) is significantly reduced at moderate and high I L . 2. The feedback ( β is the feedback factor) is strong at moderate I L and weak at both low and high I L .
Parameters of WCF Regulator Case I: Large C L R O Case II: Moderate C L R O Case III: Small C L R O Parameter Low I L Moderate I L High I L Feedback Weak Strong Weak g g R R 1 m 3 mf 2 P g g g g R R R R A m 1 m 2 m 3 mp 1 2 P O DC z g C mc c 1 p 1 C R 1 2 C R C g g g R R R R 3 dB L O L O c m 2 m 3 mp 1 2 P O p g C C g R C R 2 g C C g R C R g g g g R R C C mc c P mc P m 1 mc c P mc P m 1 m 2 m 3 mp mc 2 P m L 2,3 f p C C g R C C C R R C C R R 4,5 f c P mc P c 2 P 2 P 2 P 2 P Q C C g R C g R 2 C C g R C g R C g C g g g R R p c P mc P m mc 1 c P mc P m mc 1 L mc m m 2 m 3 mp 2 P 2,3 f Q C C g R C R C C R C R C R p c P mc P 2 2 c P P 2 2 P P 4,5 f C C g 2 g g g g g R R R C m 1 m 2 m 3 mp 1 2 P L m 1 c m 1 c UGF Due to the WCF technique, |p 4,5 | f can be pushed to a higher frequency. The stability can be achieved.
Circuit of WCF Regulator V DD S B N P M 3 M 4 M 9 R X M 12 M a1 M a2 M P C c V OUT N 2 M 5 M 6 V REF C m M 11 C B M 1 M 2 M a3 N 1 C L R L N 0 R B V B V B M 13 M 0 M 7 M 8 M 10 M a5 M a4 Weighted Current Feedback (WCF) Block 1 st Gain Stage 2 nd and 3 rd Gain Stage WCF, Power transistor, overshoot reduction, and output stage X. L. Tan, S. S. Chong, P. K. Chan, and U. Dasgupta, “A LDO Regulator with Weighted Current Feedback Technique for 0.47 nF- 10 nF Capacitive Load ” IEEE J. Solid-State Circuits , vol. 49, no. 11, Nov. 2014.
Loop Gain and Phase Responses (a) (b) Stable for C L = 470 pF and 10 nF. Minimum PM = 45 o , Minimum GM = 11 dB.
Microphotograph C c +C m Start-up 76 µ m Cap 16 µ m Bias Control Power Transistor Gen. Circuit 120 µ m 150 µ m Area = 0.0133 mm 2
Measured Transient Responses 50mA 50mA 0 100ns 100ns 0 100ns 100ns C L = 470pF C L = 1nF 29mV 29mV 113mV 1µs 1µs 50mV 109mV 50mV (a) (b) 50mA 50mA 0 0 100ns 100ns 100ns 100ns C L = 10nF C L = 3.3nF 32mV 27mV 1µs 1µs 72mV 98mV 50mV 50mV (c) (d)
Performance Comparison JSSC TCAS-I JSSC JSSC TCAS-I TCAS-II TCAS-I TCAS-I TCAS-II JSSC Parameter 2005 2007 2010 2010 2012 2012 2012 2013 2013 2014 no. 4 no.9 no. 2 no. 9 no. 5 no. 1 no. 9 no. 4 no. 6 no. 11 Technology ( μm ) 0.09 0.35 0.35 0.09 0.35 0.35 0.35 0.065 0.11 0.065 Chip Area (mm 2 ) 0.098 0.12 0.155 0.019 0.0987 0.064 0.4 0.017 0.21 0.0133 V IN (V) 1.2 3 0.95-1.4 0.75-1.2 1.2 2.5-4 1.2-1.5 1.2 1.8-3.8 0.75-1.2 V OUT (V) 0.9 2.8 0.7-1.2 0.5-1 1 2.35 1 1 1.6-3.6 0.55 Dropout Voltage (mV) 300 200 200 200 200 150 200 200 200 200 I Q ( μA ) 6000 65 43 8 28-380.1 7 45 0.9-82.4 41.5 15.9* - 487 I OUT (max) (mA) 100 50 100 100 100 100 50 100 200 50 Total On-Chip Cap. (pF) 600 21 6 7 10 7.5 41 4.5 43.2 4.1 Load Cap. Range (F) 600p 0-100p 0, 100p, 1n 0-50p 0-100p 0-100p 0-1n 0-100p 40p 470p-10n Line Reg. (mV/V) N/A 23 N/A 3.78 0.39 1 N/A 4.7 8.9 4 Load Reg. (mV/mA) 1.8 0.56 0.4 0.1 0.0782 0.08 N/A 0.3 0.108 0.18 PSR @1kHz (dB) N/A -57 N/A -44 -49.8 N/A N/A -58(@10kHz) N/A -51 Settling Time (μs) N/A 15 3 5 N/A ~0.15 ~4 6 0.65 0.25 I L(min) (mA) † 0 0 1 3 0 0.05 1 0 0.5 0 1 ΔI OUT (mA) 100 50 99 97 100 99.95 49 100 199.5 50 49 ΔV OUT (mV) 90 90 70 114 105 243 70 68.8 385 113 24 Edge Time ( μs ) 0.0001 1 1 0.1 1 0.5 1 300 0.5 0.1 0.1 Edge Time Ratio K 1 10000 10000 1000 10000 5000 10000 3000 5000 1000 1000 FOM 0.0054 1.17 0.304 0.0094 0.294 0.085 0.643 0.0019 0.4 0.036 0.0079 * Quiescent current includes the current consumption of bias circuit. † The minimum I L used to test the transient performance.
Conclusion 1. A weighted current feedback technique is proposed in OCL- LDO Regulator. 2. Due to the smart control of the output impedance of the inter gain stage, the regulator can achieve a good stability, fast speed and high accuracy. 3. The comparison results have shown the WCF LDO regulator achieves a comparable or better FOM with respect to other reported designs whilst achieving wide range of C L driving ability.
Acknowledgment Thank MediaTek for the sponsorship of scholarship as well as the chip fabrication
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