A 90nm Low-Power GSM/EDGE Multimedia- Enhanced Baseband Processor with 380MHz ARM9 and Mixed-Signal Extensions Steffen Buch 1) , Thomas Lüftner 1) , Jörg Berthold 1) , Christian Pacha 1) , Georg Georgakos 1) , Guillaume Sauzon 1) , Olaf Hömke 1) , Jurij Beshenar 3) , Peter Mahrla 1) , Knut Just 1) , Peter Hober 1) , Stephan Henzler 1,5) , Doris Schmitt-Landsiedel 5) , Andre Yakovleff 2) , Axel Klein 1) , Richard Knight 4) , Pramod Acharya 1) , Hamid Mabrouki 2) , Goulhamid Juhoor 2) , Matthias Sauer 1) 1) Infineon Technologies, Munich, Germany 2) Infineon Technologies, Sophia Antipolis, France 3) Infineon Technologies, Xian, China 4) Infineon Technologies, Bristol, United Kingdom 5) Technical University of Munich, Germany 1
Outline ! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion 2
Outline ! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion 3
Target Application: Mid-Range Feature Phones ! Baseband processor is Sec. Display Main core component of platform Display ! Main use cases: 1 2 3 MPxl FM Radio 4 5 6 Camera 7 8 9 * 0 # 3G RF MMC Transceiver Application Enhanced – Phone in standby F Baseband Processor SIM Card SIM Card E U-GOLD M 2G RF S-GOLD 3 3G L1 Transceiver – Voice call (S-GOLD 3 + Co-Processor SDRAM SPINNER1.1/1.1CR) stacked Bluetooth Engine – Music replay Flash Power A-GPS Management Engine IC – Video record/replay System Connector WLAN Engine – Video telephony Battery IrDA Transceiver Signaling Backlight Vibrator – Data transfer LEDs Sensors – Gaming 4
Outline ! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion 5
BB Processor Overview ! CMOS technology – 90nm mixed-signal low-power – Dual gate-oxide for core devices – Triple well concept ! ARM926 for protocol stack and applications ! TEAKlite DSP subsystem for GSM/EDGE Layer 1 ! Mixed signal subsystem – High quality audio front-end 6.6mm – I/Q RF interface 6
Core Performance Measurements 500 Max. Clock Frequency f (MHz) AHB ARM 400 DSP ARM/Bus/ Mem.Cntrl. 300 200 100 0 0.80 1.00 1.20 1.40 1.60 Supply Voltage V DD (V) 7
ARM Performance for Intended Process Splits 500 Nominal Process Slow Process Fast Process Maximum Frequency f (MHz) 400 Headroom for additional 300 320MHz applications under worst case process 254MHz 200 conditions 100 0 1.0 1.1 1.2 1.3 1.4 1.5 Supply Voltage V DD (V) 8
Performance Requirements ! ARM (380MHz) and DSP Application Settings ARM DSP (300MHz) provide enough f (MHz) f (MHz) processing performance to fulfill GSM idle sleep mode 0 0 requirements paging 26 26 GSM Voice 6.60-AMR 26 52 call ! Still headroom for Music replay MP3 26 26 – use case combinations and Data E-GPRS 52 104 – currently unknown use cases download Video UMTS CS, MPEG-4 104 78 telephony (15 fps, QCIF) Camcorder MPEG-4 encode 254 52 (20 fps, QVGA) 9
Outline ! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion 10
Circuit Level Power Saving Measures 11
Implementation of Sleep-Transistor Concept 12
Retention Flip Flop ! Motivation: Store data locally for fast processor restart ! Idea: isolate retention cell from flip flop input stage ! This work: – Sense-amplifier based flip flop – Retention cell implemented in low leakage devices to eliminate gate leakage current – Isolation of the retention cell by transmission gates – Negligible delay increase due to fast switching transistors implemented in Reg-V T devices 13
Retention Flip Flop: Operation FF Performance: CLK-Q delay: t CLK-Q =150ps @ 10ps setup time,V DD =1.2V, T=110°C, slow process 14
Outline ! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion 15
System Level Power Optimization ! Scaling of clock frequency (f): clocks of main building blocks are adjusted to the use case " Reduction of dynamic power dissipation ! Scaling of core voltage (V DD CORE ): core supply voltage is adjusted to the use case " Reduction of both dynamic and static power dissipation Power dissipation = α *f*C*V DD ² + I leak (V DD )*V DD 16
‘GSM Sleep’ Configuration Controller Subsystem OFF DSP Subsystem OFF OFF D-Cache I-Cache ARM926EJ OFF Interrupt DMA Boot D-TCM I-TCM RAM 0 MHz ROM Ctrl. Unit Ctrl. Prog. Memory TEAKLite Data Memory DSP Core 0 MHz OFF Multi Layer Advanced High Speed Bus (AHB) IR Memory OFF for EDGE Bridge Bridge Bridge Bridge DSP Peripherals: Multimedia Interrupts, Timer, Application & I/O GSM Cipher, and I/O System Ctrl., Interfaces: Shared Equalizer, GSM Syst. Interfaces: Power Mgmt. Camera, RAM Channel Decoder, Peripherals Display, Clock Gen. Crypto Box, BB Receive MMC Fast IrDA 8PSK/GMSK Mod. OFF OFF 32kHz Stand-By Domain Analog Macro: Audio FE, RF Interface Power VDD VDD I/O 1 VDD I/O 2 VDD CORE VDD PLL VDD RTC ANALOG Supplies OFF 1.05V 0V 1.35V 0V 17
‘GSM Paging’ Configuration Controller Subsystem ON DSP Subsystem PARTLY ON D-Cache I-Cache ON PARTLY ARM926EJ Boot Interrupt DMA ON D-TCM I-TCM RAM 26 MHz ROM Ctrl. Unit Ctrl. Prog. Memory TEAKLite Data Memory DSP Core 26 MHz OFF Multi Layer Advanced High Speed Bus (AHB) IR Memory OFF for EDGE Bridge Bridge Bridge Bridge DSP Peripherals: Multimedia Interrupts, Timer, Application & I/O GSM Cipher, and I/O System Ctrl., Interfaces: Shared Equalizer, GSM Syst. Interfaces: Power Mgmt. Camera, RAM Channel Decoder, Peripherals Display, Clock Gen. Crypto Box, BB Receive MMC Fast IrDA 8PSK/GMSK Mod. OFF OFF 26MHz Stand-By Domain Analog Macro: Audio FE, RF Interface Power VDD VDD CORE VDD RTC VDD I/O 1 VDD I/O 2 VDD PLL ANALOG Supplies ON 1.05V 0V 1.35V 2.5V 18
‘GSM Voice Call’ Configuration 19
‘E-GPRS Data Download’ Configuration 20
‘Camcorder’ Configuration 21
Outline ! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion 22
Measured ARM9 Power Dissipation 140 26MHz High 130MHz Performance 120 254MHz Example: Power Dissipation P (mW) 100 -49% reduction by frequency scaling from 80 254MHz to 130MHz Medium 60 Performance -38% reduction by voltage scaling from 40 1.35V to 1.05V 20 Low Performance 0 0.9 1 1.1 1.2 1.3 1.4 1.5 Supply Voltage VDD (V) 23
Measured Power Versus Applications Power dissipation of Core and PLL voltage domains [mW] 200 180 160 140 120 100 80 60 40 20 0 y d y e g l r l a e a n a d n l C o d o o p i g r l h M e n o a e p R w c P c e p m o i l o c e M e D i a V e s T S C l u a S M o G M t e a M S d D 3 G S i P V S G M R P G - E 24
Outline ! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion 25
Conclusion Presented GSM/EDGE BB Chip in 90nm demonstrates ! High performance ARM9: 380MHz @ 1.35V – Enabling next generation mobile phone applications ! Use case driven implementation of power saving features in a novel combination – Standby domains and SRAMs in low leakage devices – Sleep transistors to switch off mixed-V T domains – Retention flip-flops – Frequency scaling – Voltage scaling 26
Backups 27
90nm CMOS Core Devices at V DD =1.2V Regular-V t Low Leakage Device Device nFET/pFET nFET/pFET Poly Gate Length (nm) 70 90 V t,sat (mV) 370/290 550/513 Oxide Thickness t ox (nm) 1.6 2.2 On-Current ( µ A/ µ m) 680/290 350/155 Off-Current (pA/ µ m) 300 5 6 Level Metallization, 4 Thin Metal Levels, Triple Well on Non-Epi Substrate 28
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