IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 1/23 A 100 µ A/Ch Fully-Integrable Lock-in Multi-Channel Frontend for Infrared Spectroscopic Gas Recognition S. Sutula, C. Ferrer and F. Serra-Graells stepan.sutula@imb-cnm.csic.es Integrated Circuits and Systems (ICAS) Instituto de Microelectrónica de Barcelona, IMB-CNM(CSIC) June 2010 S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 2/23 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 CMOS Integration and Experimental Results 7 Conclusions S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 3/23 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 CMOS Integration and Experimental Results 7 Conclusions S. Sutula et al. IMB-CNM(CSIC)
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IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 5/23 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 CMOS Integration and Experimental Results 7 Conclusions S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 6/23 ROIC Channel Architecture ◮ High programmability f c (2bit) progin I bias (2bit) Config. event Register ◮ No external progout + V th components G m (2bit) G (2bit) C int 1 (� bit) V amp up datain V int ◮ Built-in bias V sens 20bit event R sens Counter I eff dataout generators for low down Bias & ref. - V th generator crosstalk A/D Converter ◮ Digital only interface V com V blind V lockin ◮ External lock-in synchronization ∆ V sens = I bias ∆ R sens ◮ Dedicated blind channel for cancellation of common disturbing signals ◮ Individual configuration register per channel S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 7/23 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 CMOS Integration and Experimental Results 7 Conclusions S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 8/23 Pre-Amplification and Filtering ◭ Sub-Hz high-pass specs I tun V tun ◭ Independent gain and corner M2 P £ programmability required M1 ◮ Highly linear cap amplifier: C B G = ∆ V amp ∆ V sens = C A C B init ◮ Subthreshold MRC filtering: C A V sens V amp I tun ( PTAT ) f co = 1 − Vcorner f c = f co e Ut 2 π C B U t ◮ Fast initialization switch + V corner V ref S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 9/23 Pre-Amplification and Filtering ◮ Gain tuning by P scaling I tun V tun ◮ Multi-decade filter log tuning: M2 P £ V corner = M ∆ V corner = MU t ln ( NK ) M1 f co f c = ( NK ) M C B f c × 10 ± 3 ⇔ V corner ± 173mV at 25 o C init 1 : N 1 : N C A V sens V amp M £ M1 M2 1 V ref K 1 K + V corner V ref ¢ V corner V corner S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 10/23 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 CMOS Integration and Experimental Results 7 Conclusions S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 11/23 Blind Cancellation and Lock-in Demodulation ◮ Differential to single ended M7 M8 ◮ Voltage-to- current conversion I ota ◮ Lock-in demodulation I eff V amp V blind M1 M2 + V ref ◮ Low-power subthreshold OTA : PDM stage V lockin of the ADC ∆ V amp = I ota I eff G m = 2 nU t ∝ U t M4 M3 M5 M6 I ota ∝ I S = 2 n β U 2 t (cascode topology not shown) ◮ Current-domain lock-in demodulation by cross-coupling ◮ Voltage log compression allows fast switching at low-power S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 12/23 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 CMOS Integration and Experimental Results 7 Conclusions S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 13/23 Integrating A/D Conversion event ◮ PDM noise shaping + V th C int 1 (� bit) ◮ Digital counter as low-pass filter up datain V int 20bit event Counter ◮ Asynchronous operation for very I eff dataout down low-power and low-crosstalk - V th Pulse density modulation Digital filtering S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 14/23 Integrating A/D Conversion init ◮ PDM noise shaping C int V ref + V th ◮ Digital counter as low-pass filter I eff up V int ◮ Asynchronous operation for very event low-power and low-crosstalk event down ◮ Loss-less analog integrator with CDS C reset CDS / V - V ref th for high-linearity and noise reduction: V ref I eff f PDM = C int V th S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 15/23 Integrating A/D Conversion init ◮ PDM noise shaping C int V ref + V th ◮ Digital counter as low-pass filter I eff up V int ◮ Asynchronous operation for very event low-power and low-crosstalk event down ◮ Loss-less analog integrator with CDS C reset CDS / V - V ref th for high-linearity and noise reduction: V ref I eff f PDM = V ref C int V th M1 M3 ◮ Built-in threshold comparator: up down V th = nU t ln X M4 M5 1 X X 1 ◮ Thermal compensation of G m : V int n adc = T samp f PDM = C A G m T samp q adc = ⌊ n adc ⌋ C int ∆ R sens C B V th S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 16/23 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 CMOS Integration and Experimental Results 7 Conclusions S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 17/23 CMOS Integration and Experimental Results blind 10�full�channels channel channel for�crosstalk�study blocks ◮ 0.35 µ m 2P4M CMOS channel module test chip ◮ Main design parameters : C A = 20 pF C B = { 0 . 1 , 0 . 2 , 0 . 4 , 1 } pF K = 10 N = { 1 , 11 } sensor config. M = 3 bias register I tun = 100 nA async. high-pass counter I ota = { 1 , 2 , 5 , 10 } µ A pre-amp V th = 120 mV reference�generator PDM 100 m ¹ T pulse = 500 ns ◮ Access to intermediate stages S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 18/23 CMOS Integration and Experimental Results 50 40 ◮ Sub-Hz pre-amplifier sens [dB] 11 10 01 corner<1:0>=00 30 independent tuning j 20 (16 configurations) V 10 /¢ 0 amp V -10 ¢ j -20 -30 50 11 40 10 sens [dB] 01 30 gain<1:0>=00 j 20 V 10 /¢ amp 0 V -10 ¢ j -20 -30 0.1 1 10 100 1k 10k 100k Frequency [Hz] S. Sutula et al. IMB-CNM(CSIC)
IEEE ISCAS 2010 Intro Channel Preamp Blind-Lock ADC Results Conclusions 19/23 CMOS Integration and Experimental Results 1 2 T pulse ◮ Sub-Hz pre-amplifier 1M independent tuning (16 configurations) ◮ Highly linear PDM 100k up to pulse width f PDM [Hz] 11 hard limit 10 10k 01 transc<1:0>=00 1k 0.1 1 10 100 ¢ [mV] V amp for cint<0>=0 S. Sutula et al. IMB-CNM(CSIC)
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