182.694 Microcontroller VU Martin Perner SS 2014 Featuring Today: Digital Communication 160 Submission Application 1 ◮ You need to show your final version of the application to a tutor. ◮ This has to be done in a assigned slot (10 minutes)! ◮ By default you are expected to submit in the week of the deadline, during your assigned tutorslot. ◮ If you want to submit in the week before or in an other slot, you must follow the following procedure: ◮ Choose another (free) slot in the list. ◮ Check the free box in a slot in your actual tutorslot! 161 Submission Application 1 ◮ You can use the libraries provided by us for the hardware, but you will not get points for these modules if you do! ◮ Print the protocol cover sheet, sign it and give it to the tutor. ◮ The tutor will not only check if your application works, but also ask you some questions about the hardware and your code. ◮ The uploaded archive must follow the template, as provided by us on the homepage, in front of the tutor! ( < matrnr > /Application and < matrnr > /Protocol, including < matrnr > /Protocol/Protocol.pdf) ◮ The deadline is firm, i.e., no late submissions. 162
Submission Application 1 ◮ Do not speculate that you will get enough points for application 1. ◮ We will need a few weeks to correct the protocols! ◮ There are exams from other courses in the lab. During this time you may not be able to use the lab. Check the timetable at the TILab homepage! 163 Application 1 ◮ Are there any questions? ◮ Already started with the theory task? ◮ You should use a source control management system. ◮ For example: git ◮ git bisect may come in handy when something ’just’ stopped working. ◮ Don’t forget that the second exam is on the day after the application deadline! 164 Upcoming Dates 7.5. TinyOS Lecture by Manfred Schwarz 14.5. Recitation for the second Exam. This is also the last lecture. 15.5. Application 1 Deadline 16.5. Second Exam On the following Wednesdays we will be in the lab at the time of the lecture. There will be no explicit recitation for the thrid exam; just an informal overview on the 25.6. in the lab. 165
Weekly Training Objective ◮ Already done 3.3.1 Interrupt & callback demo 3.4.1 Input capture 3.6.1 UART receiver 3.6.2 UART sender 3.9.1 Keypad ◮ This week 3.4.4 PWM signals and glitches 3.6.4 TWI (I 2 C) 3.8.2 Button debouncing 3.8.4 LCD ◮ Next week 3.5.2 Noise 3.5.3 Prescaler and accuracy 3.7.5 Dynamic memory analysis 3.10.4 Scrolling text 166 The OSI Model The 7 layer OSI Model allows to assign every component involved in the communication process to a certain layer. Application Presentation Session Transport Network Data link Physical 167 The OSI Model The 7 layer OSI Model allows to assign every component involved in the communication process to a certain layer. Application Presentation Application layer Session Transport Network Data Data link layer Physical 167
The OSI Model The 7 layer OSI Model allows to assign every component involved in the communication process to a certain layer. Application Presentation Data Session Transport Segments Network Packet Data link Frame Physical Bit 167 The OSI Model The 7 layer OSI Model allows to assign every component involved in the communication process to a certain layer. Application HTTP Presentation XML Session PPTP Transport TCP Network IPv4 Data link MAC Physical IEEE 802.3 167 Layer 1 – Physical Responsible for the actual transfer of the data bits. Media Types Wired Wireless 168
Layer 1 – Physical Responsible for the actual transfer of the data bits. Media Types Wired Wireless 389.146 Introduction a short overview to Telecommunication 168 Communication Between Two Endpoints µC µC We will now dive into the topic of media access in digital communication. 169 Single Line µC µC 170
Single Line µC µC Is there a reference level? 170 Single Line µC µC Is there a reference level? Recall exercise 2.2.2 Input with floating pins 170 Analogy: Single Line 1 1 0 0 Consider to following analogy two mechanical levers in gravity-free environment. 171
Analogy: Single Line 1 0 1 0 Left lever sets ’0’ but right lever reads still ’1’. Equivalent to floating pins. 172 Single Line and Ground µC µC No “default” state; what happens on startup? Impact of noise? 173 Analogy: Single Line and Ground 1 1 0 0 Fixing the levers to a common plate. 174
Analogy: Single Line and Ground 1 1 0 0 Bidirectional sending could result in conflicting driver ⇒ large current flowing and no transmission 175 Single Line, Ground and Pull-Up µC µC No output needed to send a ’1’. 176 Analogy: Single Line, Ground and Pull-Up X X 0 0 A weak spring keeps the bar in the high state. 177
Analogy: Single Line, Ground and Pull-Up X X 0 0 It is not possible to determine who pulled the value to 0! 178 Single Line, Ground and Pull-Up µC µC No output needed to send a ’1’. How can we do that when we ◮ do not want to writing ’0’ at the port and ◮ do not want to have a current flowing when one participant pulls the bus down? 179 Tri-State OE In Out Tri-state, three-state logic, open collector, open drain, . . . describe the same thing: ◮ A port that has the usual 0 and 1 (forwarding In to Out ), ◮ but also third state, the Hi-Z state ( OE disabled). In the Hi-Z (high-impedance) state the ports influence to the rest of the connected circuit is removed. 180
Single Line, Ground and Pull-Up µC µC ◮ Tri-state output needed instead of ’1’. ◮ Pull-up introduces recessive state. ◮ Default level is high. writing a ’0’ will bring the bus to ’0’; due to the weak pull-up only a small current will flow. ◮ Can be used for arbitration: ’0’ is dominant. ◮ Low data rate or cable length, as signal needs to propagate (especially if used for arbitration!). 181 Single Line, Ground and Driver ◮ With increasing wire length, the µC alone might not be powerful enough to keep a constant/stable voltage on the whole length of the wire. ◮ Or a different voltage level/media conversion is desired. ◮ Therefore drivers can be placed between the port of the µC and the cable. 182 Generic Approaches – Basic Line Codes Why would we not just transmit ’0’/’1’? ◮ No shared clock between the sender/receiver ⇒ loss of synchronization. ◮ We want to achieve clock regeneration! ◮ Avoid long consecutive patterns of the same value. ◮ Can avoid DC component of the signal. ◮ Allows a AC coupling between transfer medium and transceiver. ◮ . . . 183
Non-Return-To-Zero 1 0 0 1 1 1 1 0 1 1 Data Clock Signal The direct way. 184 Non-Return-To-Zero Inverted Data 1 0 0 1 1 1 1 0 1 1 Clock Signal Zero No transition. One Transition at half-clock. 185 Bit Stuffing ◮ Assume that the clock at the receiver and the sender drift. ◮ What happens after a long phase without transition? ◮ They can drift apart and lose synchronization ⇒ bit loss ◮ Solution: add a transition after a (protocol) specific amount of non-transition symbols. ◮ Allows resynchronization of receiver onto sender. 186
Bit Stuffing Example (NRZ with bit stuffing after 3 bits) 1 0 0 1 1 1 BS 1 0 1 1 Data Clock Signal 187 Bit Stuffing Can we omit the stuffing bit if the next bit causes a transition? 188 Bit Stuffing Example (NRZ with bit stuffing after 3 bits, omit stuffing if next symbol has transition) 1 0 0 1 1 1 0 1 1 0 Data 1 Clock Signal 189
Bit Stuffing Example (NRZ with bit stuffing after 3 bits, omit stuffing if next symbol has transition) 1 0 0 1 1 1 0 1 1 0 Data 1 Data 2 1 0 0 1 1 1 BS 1 1 0 Clock Signal 190 Bit Stuffing Can we omit the stuffing bit if the next bit causes a transition? No, we can not! Otherwise there is no way to distinguish between a stuffing bit and a valid signal change! 191 Return-To-Zero Data 1 0 0 1 1 1 1 0 1 1 Clock Signal ◮ Uses 3 signal levels: +1 , 0 , and − 1 . ◮ At half-clock return to 0 . ◮ Allows constant clock regeneration at the cost of bandwidth. 192
Manchester Data 1 0 0 1 1 1 1 0 1 1 Clock Signal ◮ Similar to return-to-zero but only 2 signal levels. ◮ Data = Clock XOR “Manchester Value” The Manchester Value (of a single bit) used depends on the standard, the one used above is used in IEEE 802.3. ◮ DC–balanced (if signal levels are ± X V). ◮ But again, we lose of half the bandwidth. 193 DC–balanced Encoding 8b/10b Encoding ◮ Use one 10 bit symbol to encode 8 data bits. ◮ DC–balanced in the long run ( ± 1 disparity/offset at end of a symbol). ◮ Current disparity can influence the choice of the next symbol, i.e., there may be multiple symbols for the same data bits. There are also other encodings with different symbol length. 194 Comparison NRZ NRZI RZ Manchester 8b/10b 1 / 2 1 / 2 8 / 10 bandwidth utilization ≈ 1 ≈ 1 clock regeneration × ∼ � � � bit stuffing required � ∼ × × × required signal levels 2 2 3 2 2 195
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