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UT DA Power Grid Reduction by Sparse Convex Optimization Wei Ye 1 - PowerPoint PPT Presentation

Sep 02, 2023 •559 likes •796 views

UT DA Power Grid Reduction by Sparse Convex Optimization Wei Ye 1 , Meng Li 1 , Kai Zhong 2 , Bei Yu 3 , David Z. Pan 1 1 ECE Department, University of Texas at Austin 2 ICES, University of Texas at Austin 3 CSE Department, Chinese University of

  1. UT DA Power Grid Reduction by Sparse Convex Optimization Wei Ye 1 , Meng Li 1 , Kai Zhong 2 , Bei Yu 3 , David Z. Pan 1 1 ECE Department, University of Texas at Austin 2 ICES, University of Texas at Austin 3 CSE Department, Chinese University of Hong Kong

  2. On-chip Power Delivery Network t Power grid › Multi-layer mesh structure › Supply power for on-chip devices t Power grid verification › Verify current density in metal wires (EM) › Verify voltage drop on the grids › More expensive due to increasing sizes of grids » e.g., 10M nodes, >3 days [Yassine+, ICCAD’16] 1

  3. Modeling Power Grid t Circuit modeling › Resistors to represent metal wires/vias › Current sources to represent current drawn by underlying devices › Voltage sources to represent external power supply › Transient: capacitors are attached from each node to ground t Port node: node attached current/voltage sources t Non-port node: only has internal connection Voltage source Current source Port node Non-port node 2

  4. <latexit sha1_base64="zHlfSxuDi4HaHMLIvOLEdVWXZac=">AC1HicbVHLjtMwFHXCawivAks2V1SgQSpVMkICFiONYMOCxSBRWqmJIse56biJnTR2gMryCrHly/gBfoMvwO1EBaZzJMtH5z51btZUXOkw/OX5V65eu37j4GZw6/adu/cG9x98UnXMpywuqrbWUYVlziRHNd4axpkYqswmlWvt3Ep5+xVbyWH/W6wUTQheQFZ1Q7KR38DKDH+9Tw0dLC8U6JM1xwaZhr+xO3UVJ1JTjqCEWOIKuIXFIR+Vz0bwFOLVqM5xBq/asMLsMDhGJYQx3t9nm+qlq5qH5f32U5b/t0SZd7vmA6G4TjcAvZJ1JMh6XGaDn7Hec06gVKzio1j8JGJ4a2mrMKbRB3ChvKSrAuaOSClSJ2bpu4YlTcijq1j2pYav+W2GoUGotMpcpqD5TF2Mb8bLYvNPFq8Rw2XQaJTsfVHQV6Bo2J4Sct8h0tXaEspa7XYGd0ZYy7Q4dOHu+sFoI6myJhZ1HifvcjKw8jawJkUXbRkn0yOxq/H0YcXw5M3vVsH5BF5TA5JRF6SE/KOnJIJYd6RN/Ool/lT3/rf/O/nqb7X1zwk/8H/8QfetMys</latexit> <latexit sha1_base64="zHlfSxuDi4HaHMLIvOLEdVWXZac=">AC1HicbVHLjtMwFHXCawivAks2V1SgQSpVMkICFiONYMOCxSBRWqmJIse56biJnTR2gMryCrHly/gBfoMvwO1EBaZzJMtH5z51btZUXOkw/OX5V65eu37j4GZw6/adu/cG9x98UnXMpywuqrbWUYVlziRHNd4axpkYqswmlWvt3Ep5+xVbyWH/W6wUTQheQFZ1Q7KR38DKDH+9Tw0dLC8U6JM1xwaZhr+xO3UVJ1JTjqCEWOIKuIXFIR+Vz0bwFOLVqM5xBq/asMLsMDhGJYQx3t9nm+qlq5qH5f32U5b/t0SZd7vmA6G4TjcAvZJ1JMh6XGaDn7Hec06gVKzio1j8JGJ4a2mrMKbRB3ChvKSrAuaOSClSJ2bpu4YlTcijq1j2pYav+W2GoUGotMpcpqD5TF2Mb8bLYvNPFq8Rw2XQaJTsfVHQV6Bo2J4Sct8h0tXaEspa7XYGd0ZYy7Q4dOHu+sFoI6myJhZ1HifvcjKw8jawJkUXbRkn0yOxq/H0YcXw5M3vVsH5BF5TA5JRF6SE/KOnJIJYd6RN/Ool/lT3/rf/O/nqb7X1zwk/8H/8QfetMys</latexit> <latexit sha1_base64="zHlfSxuDi4HaHMLIvOLEdVWXZac=">AC1HicbVHLjtMwFHXCawivAks2V1SgQSpVMkICFiONYMOCxSBRWqmJIse56biJnTR2gMryCrHly/gBfoMvwO1EBaZzJMtH5z51btZUXOkw/OX5V65eu37j4GZw6/adu/cG9x98UnXMpywuqrbWUYVlziRHNd4axpkYqswmlWvt3Ep5+xVbyWH/W6wUTQheQFZ1Q7KR38DKDH+9Tw0dLC8U6JM1xwaZhr+xO3UVJ1JTjqCEWOIKuIXFIR+Vz0bwFOLVqM5xBq/asMLsMDhGJYQx3t9nm+qlq5qH5f32U5b/t0SZd7vmA6G4TjcAvZJ1JMh6XGaDn7Hec06gVKzio1j8JGJ4a2mrMKbRB3ChvKSrAuaOSClSJ2bpu4YlTcijq1j2pYav+W2GoUGotMpcpqD5TF2Mb8bLYvNPFq8Rw2XQaJTsfVHQV6Bo2J4Sct8h0tXaEspa7XYGd0ZYy7Q4dOHu+sFoI6myJhZ1HifvcjKw8jawJkUXbRkn0yOxq/H0YcXw5M3vVsH5BF5TA5JRF6SE/KOnJIJYd6RN/Ool/lT3/rf/O/nqb7X1zwk/8H/8QfetMys</latexit> <latexit sha1_base64="zHlfSxuDi4HaHMLIvOLEdVWXZac=">AC1HicbVHLjtMwFHXCawivAks2V1SgQSpVMkICFiONYMOCxSBRWqmJIse56biJnTR2gMryCrHly/gBfoMvwO1EBaZzJMtH5z51btZUXOkw/OX5V65eu37j4GZw6/adu/cG9x98UnXMpywuqrbWUYVlziRHNd4axpkYqswmlWvt3Ep5+xVbyWH/W6wUTQheQFZ1Q7KR38DKDH+9Tw0dLC8U6JM1xwaZhr+xO3UVJ1JTjqCEWOIKuIXFIR+Vz0bwFOLVqM5xBq/asMLsMDhGJYQx3t9nm+qlq5qH5f32U5b/t0SZd7vmA6G4TjcAvZJ1JMh6XGaDn7Hec06gVKzio1j8JGJ4a2mrMKbRB3ChvKSrAuaOSClSJ2bpu4YlTcijq1j2pYav+W2GoUGotMpcpqD5TF2Mb8bLYvNPFq8Rw2XQaJTsfVHQV6Bo2J4Sct8h0tXaEspa7XYGd0ZYy7Q4dOHu+sFoI6myJhZ1HifvcjKw8jawJkUXbRkn0yOxq/H0YcXw5M3vVsH5BF5TA5JRF6SE/KOnJIJYd6RN/Ool/lT3/rf/O/nqb7X1zwk/8H/8QfetMys</latexit> Linear System of Power Grid t Resistive grid model: 𝑀𝑤 = 𝑗 › 𝑀 is 𝑜×𝑜 Laplacian matrix (symmetric and diagonally- dominant): (P k,k 6 = i g ( i, k ) , if i = j L i,j = � g ( i, j ) , if i 6 = j › 𝑕 (,* denotes a physical conductance between two nodes 𝑗 and 𝑘 t A power grid is safe, if ∀𝑗 : 𝑤 ( ≤ 𝑊 /0 t Long runtime to solve 𝑀𝑤 = 𝑗 for large linear systems 3

  5. Previous Work t Power grid reduction › Reduce the size of power grid while preserving input- output behavior › Trade-off between accuracy and reduction size t Topological methods › TICER [Sheehan+, ICCAD’99] › Multigrid [Su+, DAC’03] › Effective resistance [Yassine+, ICCAD’16] t Numerical methods › PRIMA [Odabasioglu+, ICCAD’97] › Random sampling [Zhao+, ICCAD’14] › Convex optimization [Wang+, DAC’15] 4

  6. Problem Definition t Input: › Large power grid › Current source values t Output: reduced power grid › Small › Sparse (as input grid) › Keep all the port nodes › Preserve the accuracy in terms of voltage drop error 5

  7. Overall Flow Node and edge set generation Large graph partition For each subgraph: Node elimination by Schur complement Edge sparsification by GCD Store reduced nodes and edges 6

  8. Node Elimination t Linear system: 𝑀𝑤 = 𝑗 t 𝑀 can be represented as a 2×2 block-matrix: 𝑀 = 𝑀 33 𝑀 34 5 𝑀 34 𝑀 44 t 𝑤 and 𝑗 can be represented as follows: 𝑤 = 𝑤 3 𝑤 4 and 𝑗 = 𝑗 3 0 t Applying Schur complement on the DC system: 7 = 𝑀 33 − 𝑀 34 𝑀 44 93 𝑀 34 5 𝑀 which satisfies: 7𝑤 3 = 𝑗 3 𝑀 b L 11 L 12 L L L > L 22 12 7

  9. Node Elimination (cont’d) h d j i e b c Node Elimination a f g d d Edge Sparsification e e b b c c a a t Output graph keeps all the nodes of interest t Output graph is dense t Edge sparsification: sparsify the reduced Laplacian without losing accuracy 8

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