Propelling SAT-based Debugging using Reverse Domination Bao Le, Hratch Mangassarian, Brian Keng, Andreas Veneris University of Toronto
Outline • SAT-based Design Debugging Introduction • Motivation and Previous Work • Dominators and Reverse Dominators Non-Solution • Non-Solution Implications from Reverse Implications Domination Relationships SAT Branching • SAT Branching Scheme Scheme for Early Non-Solution • Non-Solution Detection Learning Results and Final • Experimental Results Remarks
Outline • SAT-based Design Debugging Introduction • Domination Relationships • Dominators and Reverse Dominators Non-Solution • Non-Solution Implications from Reverse Implications Domination Relationships SAT Branching • SAT Branching Scheme Scheme for Early Non-Solution • Non-Solution Detection Learning Results and Final • Experimental Results Remarks
SAT-based Design Debugging Given an erroneous circuit, a counter example of length 𝑙 , and error cardinality 𝑂: Goal: Return shortlist of potentially buggy RTL blocks ( solutions ) Blocks that can be modified to fix counter-example Procedure: An error-select variable 𝑓 𝑗 is inserted at the outputs of each RTL block. 𝑓 𝑗 = 1 disconnects block from fan-ins, making its outputs free variables 𝑓 𝑗 = 0 does not modify the circuit Enhanced circuit is replicated 𝑙 times using time-frame expansion. Initial state, primary inputs and outputs are constrained to expected behavior of counter-example. Each satisfying assignment to 𝑓 = {𝑓 1 , … , 𝑓 𝑜 } is a debugging solution The SAT solver must find all such assignments to 𝑓 using blocking clauses.
SAT-based Design Debugging Example: b 1 x 1 g 1 x 2 g 3 y 2 x 3 b 4 g 2 g 4 y 1 x 4 b 2 b 3
SAT-based Design Debugging e 1 e 4 Time-frame 1 b 1 b 4 x 1 0 g 1 x 2 g 3 0 e 1 y 2 e 4 e 1 b 1 0 b 4 x 1 x 3 0 1 g 1 g 2 x 2 g 3 g 4 1 y 1 x 4 1 b 2 1 e 2 b 3 x 3 0 e 3 g 2 y 2 g 4 y 1 1 x 4 1 b 2 1 Time-frame 2 e 2 b 3 e 3 SAT Solver returns 𝑓 4 = 1 for 𝑂 = 1; therefore, block 𝑐 4 (i.e. gate 3 ) is the bug.
SAT-based Design Debugging SAT-based Design Debugging Fault diagnosis and logic debugging using Boolean Satisfiability [Smith, Veneris, Ali, Viglas-TCAD2005] Large designs, long counter-examples pose a scalability challenge even to modern SAT solvers. Our contributions : On-the-fly discovery of implied non-solution blocks using reverse domination Goal is to prune the search space of design debugging 1.7x speed up in SAT solving time .
Outline • SAT-based Design Debugging Introduction • Motivation and Previous Work • Dominators and Reverse Dominators Non-Solution • Non-Solution Implications from Reverse Implications Domination Relationships SAT Branching • SAT Branching Scheme Scheme for Early Non-Solution • Non-Solution Detection Learning Results and Final • Experimental Results Remarks
Outline • SAT-based Design Debugging Introduction • Motivation and Previous Work • Dominators and Reverse Dominators Non-Solution • Non-Solution Implications from Reverse Implications Domination Relationships SAT Branching • SAT Branching Scheme Scheme for Early Non-Solution • Non-Solution Detection Learning Results and Final • Experimental Results Remarks
Dominators Block 𝑐 𝑘 is said to dominate block 𝑐 𝑗 if any path from a node in 𝑐 𝑗 to a primary output passes through a node in 𝑐 𝑘 . b1 b 4 b 2 b 3
Dominators Block 𝑐 𝑘 is said to dominate block 𝑐 𝑗 if any path from a node in 𝑐 𝑗 to a primary output passes through a node in 𝑐 𝑘 . b 1 b 4 b 2 b 3
Dominators Block 𝑐 𝑘 is said to dominate block 𝑐 𝑗 if any path from a node in 𝑐 𝑗 to a primary output passes through a node in 𝑐 𝑘 . b 1 b 4 b 2 b 3 Theorem [Mangassarian, Veneris, Smith, Safarpour- ICCAD’11] : b 4 dominates b 1 If 𝑐 𝑘 is a solution block, and 𝑐 𝑗 dominates 𝑐 𝑘 , then 𝑐 𝑗 is also a solution block
Dominators Block 𝑐 𝑘 is said to dominate block 𝑐 𝑗 if any path from a node in 𝑐 𝑗 to a primary output passes through a node in 𝑐 𝑘 . b 1 b 4 b 2 b 3 No block dominates b 2
Reverse Dominators A block 𝑐 𝑗 is a reverse dominator of block 𝑐 𝑘 if and only if 𝑐 𝑘 dominates 𝑐 𝑗 , denotes 𝑐 𝑗 𝐸 -1 𝑐 𝑘 . b1 b 4 b 2 b 3 Block b 1 is a reverse dominator of b 4
Non-solution Implications Definition: Block 𝑐 𝑗 is a non-solution block iff 𝑓 𝑗 = 0 for all satisfying assignments. Theorem: If 𝑐 𝑘 is a non-solution block, and 𝑐 𝑗 𝐸 -1 𝑐 𝑘 , then 𝑐 𝑗 is also a non-solution block b1 b 4 b 2 b 3 If b 4 is a non-solution block, But how would we know that b 4 is a b 1 is also a non-solution block. non-solution in the first place?
Outline • SAT-based Design Debugging Introduction • Motivation and Previous Work • Dominators and Reverse Dominators Non-Solution • Non-Solution Implications from Reverse Implications Domination Relationships SAT Branching • SAT Branching Scheme Scheme for Early Non-Solution • Non-Solution Detection Learning Results and Final • Experimental Results Remarks
Outline • SAT-based Design Debugging Introduction • Motivation and Previous Work • Dominators and Reverse Dominators Non-Solution • Non-Solution Implications from Reverse Implications Domination Relationships SAT Branching • SAT Branching Scheme Scheme for Early Non-Solution • Non-Solution Detection Learning Results and Final • Experimental Results Remarks
SAT Branching Scheme A decision tree in a SAT solver gives the order in which variables are decided upon. Consider the decision tree: r r = 1 UNSAT
SAT Branching Scheme A decision tree in a SAT solver gives the order in which variables are decided upon. Consider the decision tree: r r = 1 r = 0 for all satisfying assignment UNSAT
SAT Branching Scheme A decision tree in a SAT solver gives the order in which variables are decided upon. Consider the decision tree: r r = 1 r = 0 for all satisfying assignment UNSAT If after analyzing r = 1, SAT Solver returns no satisfying assignment and starts analyzing r = 0, clearly r = 0 for any satisfying assignment (if one exists).
Non-Solution Detection What we have so far: r r = 1 UNSAT
Non-Solution Detection What about: e i e i = 1 e i = 0 for all satisfying assignments b i is a non-solution block. UNSAT
Non-Solution Detection In general, we can incrementally detect non-solution blocks. For example: e 1 e 1 = 1 𝑓 1 = 0 for all satisfying assignment e 2 UNSAT e 2 = 1 𝑓 2 = 0 for all satisfying assignment UNSAT e i 𝑓 𝑗 = 0 for all satisfying assignment e i = 1 UNSAT • 𝑓 2 , … 𝑓 𝑗 are also detected as non-solution blocks even though they are not the root of the decision tree.
Non-Solution Detection Deciding on the error-select variables first forces the SAT solver to learn about them faster Pruning using non-solution implications can have a stronger effect
Algorithm Overview Rearrange the order such that error select variables 𝑓 appear first in the decision tree. Extract learned non-solution blocks by inspecting the decision tree. Use reverse domination relationships to learn more non-solution blocks. Add a blocking clause for each implied non-solution block.
Outline • SAT-based Design Debugging Introduction • Motivation and Previous Work • Dominators and Reverse Dominators Non-Solution • Non-Solution Implications from Reverse Implications Domination Relationships SAT Branching • SAT Branching Scheme Scheme for Early Non-Solution • Non-Solution Detection Learning Results and Final • Experimental Results Remarks
Outline • SAT-based Design Debugging Introduction • Motivation and Previous Work • Dominators and Reverse Dominators Non-Solution • Non-Solution Implications from Reverse Implications Domination Relationships SAT Branching • SAT Branching Scheme Scheme for Early Non-Solution • Non-Solution Detection Learning Results and Final • Experimental Results Remarks
Experimental Results Platform: i5 3.1Ghz, 8GB memory, 2 hour time-limit. Benchmarks: Eight Opencores circuits and three industrial designs. For each, several bugs are injected to generate debugging instances. We modified MiniSAT 2.2.0 to implement our techniques. MiniSAT vs. dbgSAT We compare to a state-of-the-art SAT-based debugger with solution implications [Mangassarian, etal- ICCAD’11 ]:
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