Update of full silicon tracking Weiming Yao (LBNL) Silicon Tracker - PowerPoint PPT Presentation

Update of full silicon tracking Weiming Yao (LBNL) Silicon Tracker Study Meeting, Sept. 23, 2016 1/4

Introduction • Chengdong and I have checked the FTD construction code seems OK (segment vs petal) • After digi, the strip z or v position is reset to the center of strip, which causes them out of boundary. • At the moment, the fiducial check is based on geometry of module, but it depends on actual hit position. 2/4

Tracking Efficiencies vs eta • Requiring P T > 1 . 0 GeV and in barrel and endcap overlap region. • Tracking eff improves after fixing the boundary and δ -ray Events Events Events Found Tracks Found Tracks Found Tracks 600 600 600 MC MC MC 500 500 500 400 400 400 300 300 300 200 200 200 100 100 100 0 1.1 0 1.1 0 1.1 0 1 2 3 0 1 2 3 0 1 2 3 Efficiency Efficiency Efficiency 1.05 1.05 1.05 1 1 1 0.95 0.95 0.95 0.9 0.9 0.9 0.85 0.85 0.85 0 1 2 3 0 1 2 3 0 1 2 3 Theta Theta Theta (b) before (c) after (d) Without delta-ray Figure: Efficiencies vs theta 3/4

To-do List • The full silicon tracking seems in a good shape. • The digi and δ -ray is next to fix. • Dan is starting to generate some zh events and the results will follow. • Instructions can be found at http://cepc.ihep.ac.cn/ cepc/cepc twiki/index.php/Pure Silicon Detector . • Given more layers of silicon, the tracking seems get slower, about twice CPU time than CEPC V1. • Will start to document the studies. 4/4