Timing Sign-off for Selective Voltage Binning Vladimir Zolotov*, Eric Foreman, Jeffrey Hemmett, Natesan Venkateswaran, Chandu Visweswariah* IBM Electronic Design Automation, USA *IBM T. J. Watson Research Center, USA March 6-7, 2014 TAU 2014, Santa Cruz, California, USA 1
Outline • Motivation • Selective voltage binning and its benefits • Timing sign-off criteria • Small number of bins • Large number of bins • Nonseprability of Vdd variations • Experimental results • Conclusions 2
Motivation • Vdd affects performance and I off leakage too – Higher Vdd – higher leakage leaky I max and higher performance • Some chips are too leaky but Vdd fast increase Vdd reduction – Lower Vdd makes leakage acceptable • Some chips are too slow but have small leakage – Higher Vdd makes performance Good too slow acceptable F • Adjusting Vdd improves yield F req 3
Selective Voltage Binning (SVB) PDF(Process) Process Fast Slow Vdd Process Fast Nominal Slow • Chips are distributed among bins according to speed of transistors • Each bin is assigned its own supply voltage to make chips sufficiently fast 4
Performance and power improvement by SVB With SVB: Without SVB: High VDD Low VDD High VDD Leakage Power Power Leakage Delay Dynamic Power Dynamic Power Nom Slow Process Fast Fast Slow Process 5
Timing Sign-off with SVB: Problem Formulation Variational space of • Check that chips can be manufactured voltage bins with required yield if they are assigned Vdd Vdd according to their voltage bins – Take into account that interconnect Bin4 wires and transistors have independent variations Bin3 • Worst case combinations of transistor and interconnect variations are low probable Bin2 • Difficult problem for deterministic timing Whole Vdd/Process Bin1 Variational space – Requires checking corners of each voltage bin • Increases number of timing runs manifold Process – Cannot get timing credit for Fast � Slow independence of transistor and interconnect variations Sources of variations • Statistical timing covers whole variational space in single run n S s a V a P a X a R – Uses functional representation of ∑ = + Δ + Δ + Δ + Δ 0 V P i i R variability i = 1 • Slack at each point of variational space can be computed by simple Sensitivities function 6
Timing Sign-Off • Timing sign-off criterion is timing slack – Setup slack is convenient metric of chip performance • Statistical timing computes slack in canonical form n – Not a single number S s a X a R ∑ = + Δ + Δ 0 i i R i = 1 • Incompatible with conventional sign-off methodology • Projection transforms statistical slack into single number n ⎛ ⎞ S s 3 | a | | a | ∑ – Deterministic (worst case) projection = − ⎜ + ⎟ 0 i R ⎝ ⎠ i 1 = n – Statistical projection (RSSIng) 2 2 S s 3 a a ∑ = − + 0 i R • Corresponds to 3 sigma (99.87%) yield i 1 = q m ⎛ ⎞ 2 2 S s 3 | a | 3 a a – Combined projection ⎜ ∑ ⎟ ∑ = − − + 0 ⎜ j ⎟ k R ⎝ ⎠ j 1 k 1 = = • Projected statistical slack makes statistical timing compatible with conventional sign-off methodology • Timing reports in conventional form 7
Small number of bins: problem formulation • Intra-bin variations are too large to be neglected – Each bin covers wide range of variations • Intra-bin process variation has truncated Gaussian distribution p Δ ( X ) GT i-th bin X Δ GT • Statistical timing computes statistical slack covering variations across all bins • Compute and check projected slack for bin corners – Faster than timing for bin corners • Guarantee having 3 sigma (99.87%) yield of each bin – Results in the same slack for all manufactured chips • Combine process and interconnect variations statistically – RSSing of process and interconnect variations 8
Truncated Gaussian projection ( ) ( ) T t a X a X a X � a X t a X a Y t t ( 99 . 87 %) = + Δ + Δ + Δ + + Δ ⇒ + Δ + Δ ⇒ + 0 GT GT 1 1 2 2 n n 0 GT GT 0 tg to be truncated Gaussian Others Gaussian parm-s Truncation Convolution RSS List Truncated parameter Distribution of other a GT X Δ a Δ Y parameters • RSS sum of Gaussians GT parameters a X a X � a n X Δ + Δ + + Δ 1 1 2 2 n into a Δ Y X • Truncate Δ GT t r t l – Filter out chips with X ∞ Δ GT f t ( ) ( t ) d Convolution outside truncation region ∫ τ φ − τ τ • Convolve truncated Gaussian a GT X Δ − ∞ GT and Gaussians RSSed a Δ Y • Project the resulted distribution 99.87% to 99.87% level – Equivalent to 3 sigma Projected value t tg Gaussian projection • Use projection tables for fast t computation of multiple slacks tg 1 f ( t ) dt ( 3 ) − in timing reports = Φ ∫ Compute t tg from 9 − ∞
SVB with small number of bins: implementation Computation of truncation Projection slack computation projection tables • Mapping: • Transform statistical slack to t b X Y Δ + Δ GT tg form suitable for table • Each table is characterized application with left and right truncation limits t l and t r s a X a X � a X + Δ + Δ + + Δ 0 GT GT 1 1 n n • Table input : sensitivity to truncated variable b ( ) s a X a Y + Δ + Δ • Table output: truncated 0 GT GT projected value t tg • Tables are generated once for ( ) s a b X Y + Δ + Δ technology node 0 GT • Find table with required – Does not affect timing run time truncation limits t l and t r • Table access time does not • Compute projection by table t depend on table size tg look up – Fixed step of input parameter • Compute projected slack Bin ranging from t l =-3 to t r =0 sigmas S s a t = + ⋅ pr 0 tg Sensitivity to truncated variable xx xx xx 10 Projected truncated value xx xx xx
SVB sign-off for large number of bins Vdd Intra-bin variation • Projection of all process corners is too inefficient – Too many bins, too many corners • Bins are very small – Intra-bin variation of Vdd and Process is small • Can be neglected – Vdd and Process are almost Process perfectly (mis-) track each other • Timing uses (anti-)correlation Fast � Slow between Process and Vdd to model SVB – Simple and efficient solution n S s a V a P a X a R – No need for multicorner ∑ = + Δ + Δ + Δ + Δ 0 V P i i R projection i = 1 – As Vdd perfectly tracks Process it became a random variable Anti-correlation • Same solution for adaptive voltage supply 11
SVB with multiple Vt families • Variations of Vt families are correlated P , P , P , … Δ Δ Δ 1 2 • However, chip sorting among bins uses only Vt family P Δ • Projection based timing sign-off assumed independence of SVB variable – Decorrelation is needed • PCA is not suitable as decorrelated variables are not measured • Decorrelation can be performed as follows: • Each variable can be represented as P P a P a P Δ Δ = Δ + Δ i i i , c i . I i , I where P , P Δ Δ i I – is independent of 2 E ( P , P ) E ( a P ) E ( a P P ) a ρ = Δ Δ = Δ + Δ Δ = i i i , c i , c i , I i , C • Covariance a = ρ i , C i Therefore 2 2 2 Var ( P ) E ( P ) a a 1 P Δ = Δ = + = Δ i i i , C i , I i • Variance of is 2 a 1 = − ρ i , I i Therefore • Applying this transformation to canonical form we remove correlation between SVB variable and other variables P Δ – Truncated Gaussian projection can be applied to SVB variable 12
Nonseparable voltage variability Delay sensitivity to process • Circuits are designed for wide range of voltages 30.00% 28.00% – Applications, voltage binning, adaptive 26.00% voltage supply, dynamic voltage scaling 24.00% • Supply voltage is not statistical but 22.00% UVT 20.00% SVT deterministic variable HVT 18.00% – Must be modeled accurately in its entire 16.00% range 14.00% 12.00% • Supply voltage affects delay variability 10.00% Vdd 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 – Linear model is too inaccurate D(V,X) • Conventional statistical timing cannot Error of model voltage variations Actual delay Linear linear model delay – Large error occurs even at corners model • Existing solutions: – Either single statistical timing run with additional design margins – Or 2 statistical timing runs at low and high voltages X • Both solutions are not sufficiently good – Sign-of timing iterates between high and low voltages V 13
Modeling deterministic nonseparable variations of Vdd • Timing quantity is modeled with bi-linier form (hyperboloid) – Voltage cross-terms model voltage influence on variability • Supply voltage is modeled deterministically – Fits voltage corners exactly • Projection to voltage values turns bi-linear form into a linear one D(V, Y) d d ΔV d ΔY d ΔVΔY = + + + 0 V Y VY D (Y) d d ΔY D (Y) d d ΔY = + = + HV 0, HV Y, HV LV 0, LV Y, LV Low voltage High voltage model model D HV (Y) D (Y) d d ΔY = + V 0, V Y, V Mid voltage model D LV (Y) Y V 14
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