Systems Interleaving + Parallelism Shankar Balachandran* Associate - - PowerPoint PPT Presentation

Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras

*Currently a Visiting Professor at IIT Bombay

Digital Circuits and Systems

Spring 2015 Week 8 Module 45

Interleaving + Parallelism

Acknowledgements

 MIT’s Open Course Contents of 6.004

Pipelining Methodology 2

Problem with Pipelining

 Slowest component becomes the bottleneck

Pipelining Methodology 3

Pipelined Components

Pipelining Methodology 4

 Pipeline the slowest component  Here, throughput = 1  Replacing a slow combinational component with a k-

pipe version may increase clock frequency

 Must account for new pipeline stages in our plan

Laundry Example

 Find a place with twice as many dryers as washers.

Pipelining Methodology 5

 Throughput = 1/30 loads/min.  Latency = 90 mins/load

Back to Our Bottleneck

 C is the slowest  Either find a pipelined

version of C

 Or interleave multiple

copies of C

Pipelining Methodology 6

Circuit Interleaving

 Copy the critical element  Alternate between copies to simulate pipelining of the

slowest component

Pipelining Methodology 7

Interleaving

Pipelining Methodology 8

Interleaving

Pipelining Methodology 9

 Clock period 0: X0 presented at input, propagates through

upper latch, C0

 Clock period 1: X1 presented at input, propagates through

lower latch, C1.

 C0(X0) propagates to register inputs.

 Clock period 2: X2 presented at input, propagates through

upper latch, C.

 C0(X0) loaded into register, appears at output.

Latency = 2 cycles

N-Way Interleaving

Pipelining Methodology 10

Combine Interleaving with Pipelining

 Shifts the bottleneck from C to F

Pipelining Methodology 11

And a Little Parallelism

 Combine Interleaving

and pipelining with parallelism

 Throughput = 2/30 =

1/15 load/min

 Latency = 90 min

Pipelining Methodology 12

Summary

 Latency (L) = time it takes for given input to arrive at

• utput

 Throughput (T) = rate at each new outputs appear  For combinational circuits: L = tPD of circuit, T = 1/L  For K-pipelines (K > 0):

 always have register on output(s)  K registers on every path from input to output  Inputs available shortly after clock i, outputs available shortly after

clock (i+K)

 T = 1/(tPD,REG + tPD of slowest pipeline stage + tSETUP)  more throughput =>split slowest pipeline stage(s)  use replication/interleaving if no further splits possible

 L = K / T

 pipelined latency >= combinational latency

Pipelining Methodology 13

End of Week 8: Module 45

Thank You

Pipelining Methodology 14