Spring 2015 Week 4 Module 19 Digital Circuits and Systems Gated Latches Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras *Currently a Visiting Professor at IIT Bombay
Gated SR Latch Clk S R Q(t+1) 1 0 0 Q(t) 1 0 1 0 1 1 0 1 1 1 1 Undefined 0 X X Q Gated Latches 2
Gated SR Latch with NAND Gates CLK S R Q(t+1) S 1 0 0 Q(t) Q 1 0 1 0 Clk 1 1 0 1 1 1 1 Undefined Q 0 X X Q R Still have problems with 11 inputs to SR latch One solution is to define the condition away: never allow both inputs to the SR to have the same value. Gated Latches
Gated D latch D (data) latch does not allow both inputs to an SR latch to have the same value. G D Q(t+1) Q(t+1) Characteristic Table 1 0 0 1 1 1 1 0 0 X Q(t) Q(t) A register is an array of D latches or flip-flops which share a common gate/clock – this is a fundamental building block for computer design. Gated Latches 4
Synchronous versus Asynchronous Sequential circuits can be. Asynchronous or. Synchronous. Asynchronous Sequential Circuits : State changes can occur at any time. Synchronous Sequential Circuits : State changes can occur only in conjunction with a reference timing signal. This signal is generally known as the clock signal of the system. For the most part, we will consider only synchronous circuits in this class. Gated Latches 5
Clocking of Synchronous Circuits: Clock signals are usually periodic. Duty cycle = ON Time / Clock Period Frequency = 1/Time Period Units are in Hz Gated Latches 6
Issues with Latches Latches are level sensitive: For example: In a D-Latch, if G is ON, multiple changes to D will be propagated to the output This can in turn result in undesirable results Gated Latches 7
End of Week 4: Module 19 Thank You Gated Latches 8
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