Systems More Sequential Circuits Shankar Balachandran* Associate - PowerPoint PPT Presentation

Spring 2015 Week 5 Module 26 Digital Circuits and Systems More Sequential Circuits Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras *Currently a Visiting Professor at IIT Bombay

Frequency Divider Q1 Q0 “ 1 ” “ 1 ” Q Q T T Q Q < < CLK CLK f Q0 f/2 Q1 f/4 More Sequential Circuits 2

3-Bit Up Counter 1 Q Q Q T T T Clock Q Q Q Q Q Q 0 1 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count 0 1 2 3 4 5 6 7 0 (b) Timing diagram More Sequential Circuits

3-Bit Down Counter 1 T Q Q Q T T Clock Q Q Q Q Q Q 0 1 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count 0 7 6 5 4 3 2 1 0 (b) Timing diagram More Sequential Circuits

Issues  Counters are asynchronous  The flipflops are not all synchronized to the same clock  A big enough width of the counter can upset the counting logic  Flip flop 0’s output delays flip flop1  Flip flop 1’s output delays flip flop 2  .  .  .  Need for a counter that works “synchronously” w.r.to clock 5

Observation Clock cycle Q Q Q 2 1 0 Q changes 1 0 0 0 0 Q changes 2 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 Question: 6 1 1 0 When should Q3 toggle? 7 1 1 1 8 0 0 0 Q0 toggles every clock cycle Q1 toggles every time Q0 changes from 1 to 0 Q2 toggles every time Q1 is at 1 and Q0 changes from 1 to 0 More Sequential Circuits 6

1 T Q T Q T Q T Q Q Q Q Q 0 1 2 3 Clock Q Q Q Q (a) Circuit Clock Q 0 Q 1 Q 2 Q 3 Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 (b) Timing diagram More Sequential Circuits 7

With Enable and Clear Enable Q Q Q Q T T T T Clock Q Q Q Q Clear_n More Sequential Circuits 8

With D Flipflops Sequential Circuits 9

Counter with Parallel Load Capability Sequential Circuits 10

Synchronous Mod-6 Counter Enable 1 0 D Q 0 0 D Q 0 1 1 0 D Q 2 2 Load Clock Clock (a) Circuit Clock Q 0 Q 1 Q 2 Count 0 1 2 3 4 5 0 1 (b) Timing diagram

Reading Exercises Sequential Circuits 12

1 T Q T Q T Q Q Q Q 0 1 2 Clock Q Q Q Asynchronous Mod-6 Counter (a) Circuit Clock Q 0 Q 1 Q 2 Count 0 1 2 3 4 5 0 1 2 (b) Timing diagram

End of Week 4: Module 26 Thank You More Sequential Circuits 14