SuperNova burst buffer ( NVMe from Zynq ) Roy Wastie University of - PowerPoint PPT Presentation

SuperNova burst buffer ( NVMe from Zynq ) Roy Wastie University of Oxford 1 17/10/19 DUNE-UK DAQ workshop

Specifcation • SSD NVMe on the PS of the ZYNQ PCIe Gen2 (4 lanes). • Data transfer rate @ 1.6GB/s for >50GB (100s). • Data source from the PL side of the ZYNQ. • DMA from PL to PS memory. • Transfer PS Memory to SSD. • The SN trigger rate?. • Empty SSD at a slower rate in background. • No Dead Time. 2 17/10/19 DUNE-UK DAQ workshop

Evaluation Board with SSD 3

SSD Read/Write Status • Tests on the ZCU102 Eval Board show that we can transfer 1.6GB/s sustained to the SSD > 50GB transferred with LINUX OS using the FIO command. • Can it maintain this will DMAing data from the PL?. 4 17/10/19 DUNE-UK DAQ workshop

Current Plans • Develop test firmware to DMA data from the PL to PS. • Develop Software on the PS to Setup/control the DMA • Develop Software on the PS to write the data to the SSD drive. 5 17/10/19 DUNE-UK DAQ workshop

SSD Write AXI GPIO AXI DMA Data Interface Frame Size S_AXI S_AXI En M_AXIS S_AXIS M_AXIS S_AXIS (Memory mapped) AXI_En Clk Interrupt Clk Clk ZYNQ PS S_AXI PCIe HP0 SSD DRAM DRAM IRQ Controller M_AXI ARM GP0 Cores 6 17/10/19 DUNE-UK DAQ workshop

DMA Test Design AXI GPIO AXI DMA Pattern Generator Frame Size S_AXI S_AXI En M_AXIS S_AXIS M_AXIS S_AXIS (Memory mapped) AXI_En Clk Interrupt Clk Clk ZYNQ PS S_AXI HP0 DRAM DRAM IRQ Controller M_AXI ARM GP0 Cores 7 17/10/19 DUNE-UK DAQ workshop

Firmware Design 8 17/10/19 DUNE-UK DAQ workshop

Bare Metal Software for ARM Host • Initializes the system (First Stage Boot Loader) • Enables the PL clocks and PS-PL AXI interfaces • Programs the AXI DMA engine • Programs the Pattern Generator through the AXI GPIO 9 17/10/19 DUNE-UK DAQ workshop