Software Programming Language Compiler/Interpreter Operating - PowerPoint PPT Presentation

Program, Application Software Programming Language Compiler/Interpreter Operating System Instruction Set Architecture Microarchitecture Hardware Digital Logic Devices (transistors, etc.) Solid-State Physics

Instruction Set Architecture (HW/SW Interface ) processor memory Instructions Instruction Encoded Names, Encodings • Logic Instructions Effects • Arguments, Results • Registers Data Local storage Names, Size • How many • Large storage Addresses, Locations • Computer

Computer Microarchitecture ( Implementation of ISA) Instruction ALU Registers Memory Fetch and Decode

HW ISA HW (HW = Hardware or Hogwarts?) An example made-up instruction set architecture Word size = 16 bits • Register size = 16 bits. • ALU computes on 16-bit values. Memory is byte-addressable , accesses full words (byte pairs). 16 registers: R0 - R15 • R0 always holds hardcoded 0 Address Contents • R1 always holds hardcoded 1 0 First instruction, • R2 – R15: general purpose low-order byte Instructions are 1 word in size. 1 First instruction, high-order byte Separate instruction memory . 2 Second instruction, Program Counter (PC) register low-order byte • holds address of next instruction to execute. ... ... 4

R: Register File M: Data Memory Reg Contents Reg Contents Address Contents 0x0 – 0x1 R0 0x0000 R8 0x2 – 0x3 R1 0x0001 R9 R2 R10 0x4 – 0x5 R3 R11 0x6 – 0x7 R4 R12 0x8 – 0x9 R5 R13 0xA – 0xB R6 R14 0xC – 0xD R7 R15 … Program Counter IM: Instruction Memory PC Address Contents 0x0 – 0x1 1. ins ß IM[PC] Processor 0x2 – 0x3 2. PC ß PC + 2 Loop 0x4 – 0x5 3. Do ins 0x6 – 0x7 HW HW ISA Abstract 0x8 – 0x9 Machine …

HW ISA HW Instructions 16-bit Encoding LSB MSB Assembly Syntax Meaning Opcode Rs Rt Rd ADD R s, R t, R d R[ d ] ß R[ s ] + R[ t ] 0010 s t d SUB R s, R t, R d R[ d ] ß R[ s ] - R[ t ] 0011 s t d AND R s, R t, R d R[ d ] ß R[ s ] & R[ t ] 0100 s t d OR R s, R t, R d R[ d ] ß R[ s ] | R[ t ] 0101 s t d LW R t, offset (R s ) R[ t ] ß M[R[ s ] + offset ] 0000 s t offset SW R t, offset (R s ) M[R[ s ] + offset ] ß R[ t ] 0001 s t offset If R[ s ] == R[ t ] then BEQ R s, R t, offset 0111 s t offset PC ß PC + offset *2 JMP offset PC ß offset *2 1000 o f f s e t (R = register file, M = memory) 7

R: Register File M: Data Memory Reg Contents Reg Contents Address Contents 0x0 – 0x1 R0 0x0000 R8 0x2 – 0x3 R1 0x0001 R9 2 R2 R10 3 0x4 – 0x5 R3 R11 0x6 – 0x7 R4 R12 0x8 – 0x9 R5 R13 0xA – 0xB R6 R14 0xC – 0xD R7 R15 … Program Counter IM: Instruction Memory PC Address Contents 0x0 – 0x1 SUB R8, R8, R8 1. ins ß IM[PC] Processor 0x2 – 0x3 BEQ R9, R0, 3 2. PC ß PC + 2 Loop 0x4 – 0x5 ADD R10, R8, R8 3. Do ins 0x6 – 0x7 SUB R9, R1, R9 HW HW ISA Abstract 0x8 – 0x9 JMP 1 Machine 0xA – 0xB HALT

HW HW microarchitecture 4 1 3 2 Instruction ALU Registers Memory Fetch and Decode Hardware implementation of the HW HW ISA

1. ins ß IM[PC] Processor Instruction Fetch 2. PC ß PC + 2 Loop 3. Do ins Fetch instruction from memory. Increment program counter (PC) to point to the next instruction. Add 2 Instruction Memory Read PC Address Instruction 12

Arithmetic Instructions Opcode Rs Rt Rd ADD R3, R6, R8 0010 0011 0110 1000 16-bit Encoding Instruction Meaning Opcode Rs Rt Rd ADD Rs, Rt, Rd R[d] ß R[s] + R[t] 0010 0-15 0-15 0-15 SUB Rs, Rt, Rd R[d] ß R[s] – R[t] 0011 0-15 0-15 0-15 AND Rs, Rt, Rd R[d] ß R[s] & R[t] 0100 0-15 0-15 0-15 OR Rs, Rt, Rd Rd ß R[s] | R[t] 0101 0-15 0-15 0-15 ... 13

Instruction Decode, Register Access, ALU Control 4 Opcode Unit Reg Write ALU Op Write Enable 4 Read Addr 1 16 Read Rs 16 4 Data 1 Read Addr 2 overflow Rt Register File ALU Instruction zero 4 Write Addr Rd 16 Read ALU result 16 Data 2 Write Data 14

Memory Instructions Opcode Rs Rt Rd SW R6, -8(R3) 0001 0011 0110 1000 Instruction Meaning Op Rs Rt Rd LW Rt, offset(Rs) R[t] ß Mem[R[s] + offset] 0000 0-15 0-15 offset SW Rt, offset(Rs) Mem[R[s] + offset] ß R[t] 0001 0-15 0-15 offset ... 15

How can we support arithmetic Memory access and memory instructions? What's shared? Control 4 Opcode Unit Reg Write ALU Op Write Enable 4 Mem Store Read Addr 1 16 Read Rs Write Enable 16 Data 1 4 Address Read Addr 2 16 Rt ALU Register File Inst 32 Data Memory Write Addr 16 Read Rt Data 2 Read Write 16 Write Data Data Data 4 4 16 Sign Rd extend (offset) 16

Choose with MUXs Mem Load Control 4 Opcode Unit Reg Write ALU Op Write Enable 4 Mem Store Read Addr 1 16 Read Rs Write Enable 16 Data 1 4 Address Read Addr 2 16 Rt ALU Register File Inst 32 Data Memory Rt 1 4 Write Addr 16 Read 0 0 Data 2 Rd Read Write 16 1 Write Data Data Data 4 16 Rd Sign (offset) extend 0 1 17

Control-flow Instructions Op Rs Rt Rd BEQ R1, R2, -4 0111 0001 0010 1110 16-bit Encoding Instruction Meaning Op Rs Rt Rd If R[s] == R[t] then PC ß PC+2 + offset*2 BEQ Rs, Rt, offset 0111 0-15 0-15 offset Else PC ß PC+2 ... 18

Compute branch target + Shift left by 1 Control 4 ALU Op Unit Reg Write + 2 Write Enable 4 Read Addr 1 Read 16 Instruction Memory Data 1 16 4 Read Addr 2 Read 16 PC ALU Address Register File Inst 32 1 4 Write Addr 16 Read 0 0 Data 2 1 Write Data 4 Sign 16 extend 19

Make branch decision MUX + Shift left by 1 Branch? Mem Load Control 4 ALU Op Unit Reg Write + 2 Write Enable Mem Store 4 Read Addr 1 Read 16 Instruction Write Enable Memory Data 1 16 4 Address Read Addr 2 Read 16 PC ALU Address Register File Inst 32 Data Memory 1 4 Write Addr 16 Read 0 0 Data 2 Read Write 16 1 Write Data Data Data 4 Sign 16 extend 0 1 21

HW HW microarchitecture: not the only implementation Single-cycle architecture • Simple, "easily" fits on a slide (and in your head). • One instruction takes one clock cycle. • Slowest instruction determines minimum clock cycle. • Inefficient. Could it be better? • How? Performance, energy, debugging, security, reconfigurability, … • Pipelining • OoO: out-of-order execution • SIMD: single instruction multiple data • Caching • Microcode vs. direct hardware implementation • … enormous, interesting design space of Computer Architecture 22