Software-Managed TRANSLATION Address Translation Bruce Jacob - PDF document

SOFTWARE- MANAGED ADDRESS Software-Managed TRANSLATION Address Translation Bruce Jacob University of Michigan Bruce Jacob and Trevor Mudge Advanced Computer Architecture Lab University of Michigan OUTLINE: Background & Motivation • Softvm Design • Experiments & Results • ADVANCED COMPUTER ARCHITECTURE LAB SOFTWARE- MANAGED ADDRESS Historical Perspective TRANSLATION Bruce Jacob MIPS: University of Michigan HW page-table-walking unnecessary • SPUR: HW storage for PTEs unnecessary • VMP: Software-controlled caches work • CONCLUSION: Can get rid of TLB altogether

SOFTWARE- MANAGED ADDRESS TLB Architecture TRANSLATION Bruce Jacob Virtual Page Number Page Offset University of Michigan TLB (CAM) DIRECT-MAPPED CACHE PFN Cache Block (Data) VPN Pr P-Tag Protection Violation? Match? AND CACHE DATA SOFTWARE- MANAGED ADDRESS TLB Miss TRANSLATION Bruce Jacob TLB Miss TLB University of Michigan CPU CACHE NO DATA Virtual Address Index Index Offset Page Frame User Table Root Table BASE

SOFTWARE- MANAGED ADDRESS SOFTVM Architecture TRANSLATION Bruce Jacob CPU University of Michigan DIRECT-MAPPED CACHE V-Tag Pr Cache Block (Data) Match? Protection Violation? AND CACHE MISS EXCEPTION CACHE DATA SOFTWARE- MANAGED ADDRESS SOFTVM Miss TRANSLATION Bruce Jacob CACHE University of TAGS Michigan CACHE MISS CPU CACHE DATA Virtual Address Index Index Offset Page Frame User Table Root Table BASE PHYSICAL & VIRTUAL ADDR PHYSICAL ADDR PHYSICAL ADDR

SOFTWARE- MANAGED ADDRESS Cost of Software Solution TRANSLATION Bruce Jacob Cost to handle TLB Miss: ~12 cycles University of Michigan Build PA & Load RPTE • Build PA & Load UPTE Insert UPTE into TLB Retry Load Cost to handle Cache Miss: ~15 cycles Build PA & Load RPTE • Build PA & Load UPTE Prepare caches for USER-DATA Build PA & Load USER-DATA Retry Load SOFTWARE- MANAGED ADDRESS Cost vs. Cache Size TRANSLATION Bruce Jacob D-CACHE HIT RATE I-CACHE HIT RATE University of COST PER CACHE MISS Michigan COST PER INSTRUCTION 180 1.2 Hit Rate and Cycles per Cache Miss 150 1.0 SOFTVM Overhead (CPI) 120 0.8 90 0.6 60 0.4 30 0.2 0 0.0 2K 4K 8K 16K 32K 64K 128 256 512 1M 2M 4M Cache Size (combined)

SOFTWARE- MANAGED ADDRESS Experiments TRANSLATION Bruce Jacob Modified 32-BIT PowerPC Architecture, University of Michigan MIPS-like Page Table Trace-Driven Simulations: L1 Cache (20): 2—256 KBytes • L2 Cache (100): 1, 2, 4 MBytes • Linesizes: 16—128 Bytes • RESULTS: Softvm: 0.1 to 5% Overhead • Mach+MIPS: 5 to 10% Overhead • Ultrix+MIPS: 2% Overhead • SOFTWARE- MANAGED ADDRESS Results TRANSLATION Bruce Jacob L1 Caches: 16/16KB D/I, 32-byte linesize University of Michigan L2 Caches: 64-byte linesize 0.030 VORTEX GCC GCC VORTEX IJPEG IJPEG 0.020 0.010 0.000 512KB 1MB 2MB 512KB 1MB 2MB L2 Data Cache Size L2 Instruction Cache Size DATA-SIDE INSTRUCTION-SIDE

SOFTWARE- MANAGED ADDRESS Potential Problem: STREAM TRANSLATION Bruce Jacob MULTIMEDIA HAS University of Michigan NO TEMPORAL LOCALITY WORST-CASE SCENARIO: Take an exception for every cache line SOLUTIONS: Prefetch buffers • Prefetch into L2 cache • Provided unmapped regions to user • SOFTWARE- MANAGED ADDRESS Design Considerations TRANSLATION Bruce Jacob LARGE VIRTUAL CACHES: University of Michigan Synonym Problem SOLUTION: Segmentation or Large ASIDs w/ Flat Address Space DRAWBACK: Increases size of cache tags

SOFTWARE- MANAGED ADDRESS Conclusions TRANSLATION Bruce Jacob TLB Elimination is Possible University of Michigan Cycle Time can DECREASE Performance can INCREASE Support for Multimedia Possible Software-Managed: FLEXIBILITY ADVANCED COMPUTER ARCHITECTURE LAB