Simulating Timed UML2 Sequence Diagrams with Timed CSP M Roggenbach - PowerPoint PPT Presentation

Simulating Timed UML2 Sequence Diagrams with Timed CSP M Roggenbach (Swansea, Wales, UK) Alexander Knapp, Liam O’Reilly, and Holger Schlingloff September 2013

What is the added value? 2 What is the added value? Timed UML2 Sequence Diagram (Ventricular Assist Device) Captures the set of “possible timed system behaviours”. Our aim: early system validation by simulation. M Roggenbach: Simulating; September 2013

This is a “first ideas” talk 3 This is a “first ideas” talk Here: • Timed Sequence Diagrams. • Simulation with Timed CSP Simulator. In the long run: • Several Timed UML2 diagrams. • Simulation / Model checking with UPPAAL, PAT, FDR2, Timed CSP Simulator, . . . to check if the various viewpoints “fit” together. M Roggenbach: Simulating; September 2013

Semantics

Semantics via Timed Automata 5 Semantics via Timed Automata • Extends semantics of untimed sequence diagrams via untimed automata by Knapp & Wuttke in 2007. • One clock per time constraint. • Annotations on the transitions: time guards & clock resets. s_1 snd(setStartUp) s_2 rcv(setStartUp) / c_1 = 0; s_3 snd(setStartUpAck) s_4 rcv(setStartUpAck) s_5 snd(setPumpParameters) s_6 rcv(setPumpParameters) [c_1 <= 30000] s_7 snd(canSetRateLeft) s_8 snd(canSetRateRight) rcv(canSetRateLeft) s_74 s_9 rcv(canSetRateRight) rcv(canSetRateLeft) snd(canSetRateRight) snd(canSetRateAckLeft) s_75 s_71 s_10 snd(canSetRateAckRight) rcv(canSetRateLeft) rcv(canSetRateRight) snd(canSetRateAckLeft) snd(canSetRateRight) s_76 s_72 s_11 rcv(canSetRateLeft) snd(canSetRateAckRight) snd(canSetRateAckLeft) rcv(canSetRateRight) rcv(canSetRateAckLeft) s_73 s_12 s_68 snd(canSetRateAckLeft) snd(canSetRateAckRight) rcv(canSetRateAckLeft) rcv(canSetRateRight) snd(setRateAck) s_13 s_65 s_69 rcv(canSetRateAckLeft) snd(canSetRateAckRight) snd(setRateAck) rcv(canSetRateRight) rcv(setRateAck) s_14 s_66 s_70 snd(setRateAck) snd(canSetRateAckRight) rcv(setRateAck) rcv(canSetRateRight) s_15 s_67 rcv(canSetRateAckRight) / c_2 = 0; rcv(setRateAck) snd(canSetRateAckRight) s_44 s_16 rcv(setRateAck) snd(canSetOtherParamsLeft) [c_2 >= 100] rcv(canSetRateAckRight) / c_2 = 0; s_17 s_45 snd(canSetOtherParamsLeft) [c_2 >= 100] rcv(canSetOtherParamsLeft) rcv(setRateAck) snd(canSetOtherParamsRight) s_63 s_18 s_46 snd(canSetOtherAckLeft) rcv(setRateAck) snd(canSetOtherParamsRight) rcv(canSetOtherParamsLeft) snd(canSetOtherParamsRight) rcv(canSetOtherParamsLeft) rcv(setRateAck) rcv(canSetOtherParamsRight) s_64 s_42 s_61 s_19 s_47 rcv(setRateAck) snd(canSetOtherParamsRight) snd(canSetOtherAckLeft) snd(canSetOtherParamsRight) snd(canSetOtherAckLeft) rcv(setRateAck) rcv(canSetOtherParamsRight) rcv(canSetOtherParamsLeft) rcv(canSetOtherParamsRight) rcv(canSetOtherParamsLeft) rcv(setRateAck) snd(canSetOtherAckRight) s_43 s_62 s_40 s_59 s_20 s_48 snd(canSetOtherParamsRight) rcv(setRateAck) rcv(canSetOtherParamsRight) snd(canSetOtherAckLeft) rcv(canSetOtherParamsRight) snd(canSetOtherAckLeft) rcv(setRateAck) snd(canSetOtherAckRight) rcv(canSetOtherParamsLeft) snd(canSetOtherAckRight) rcv(canSetOtherParamsLeft) rcv(setRateAck) rcv(canSetOtherAckRight) s_41 s_60 s_21 s_57 s_36 s_49 rcv(canSetOtherParamsRight) rcv(setRateAck) snd(canSetOtherAckRight) snd(canSetOtherAckLeft) snd(canSetOtherAckRight) snd(canSetOtherAckLeft) rcv(setRateAck) rcv(canSetOtherAckRight) rcv(canSetOtherParamsLeft) rcv(canSetOtherAckRight) rcv(canSetOtherParamsLeft) rcv(setRateAck) snd(setOtherParamsAck) s_35 s_58 s_22 s_50 s_37 s_56 snd(canSetOtherAckRight) rcv(setRateAck) rcv(canSetOtherAckRight) snd(canSetOtherAckLeft) rcv(canSetOtherAckRight) snd(canSetOtherAckLeft) rcv(setRateAck) snd(setOtherParamsAck) rcv(canSetOtherParamsLeft) snd(setOtherParamsAck) rcv(canSetOtherParamsLeft) rcv(setRateAck) s_23 s_51 s_32 s_55 s_38 rcv(canSetOtherAckRight) rcv(setRateAck) snd(setOtherParamsAck) snd(canSetOtherAckLeft) snd(setOtherParamsAck) snd(canSetOtherAckLeft) rcv(setRateAck) rcv(canSetOtherParamsLeft) rcv(setOtherParamsAck) s_24 s_52 s_33 s_39 snd(setOtherParamsAck) rcv(canSetOtherAckLeft) rcv(setRateAck) snd(canSetOtherAckLeft) rcv(setOtherParamsAck) rcv(canSetOtherParamsLeft) s_53 s_25 s_34 snd(setPumpParametersAck) rcv(setRateAck) rcv(canSetOtherAckLeft) rcv(setOtherParamsAck) snd(canSetOtherAckLeft) s_54 s_30 s_26 rcv(setRateAck) snd(setPumpParametersAck) rcv(setOtherParamsAck) rcv(canSetOtherAckLeft) s_31 s_27 rcv(setOtherParamsAck) snd(setPumpParametersAck) s_28 rcv(setPumpParametersAck) s_29 M Roggenbach: Simulating; September 2013

Encoding Timed Automata within Timed CSP 6 Encoding Timed Automata within Timed CSP • Only a subclass of timed automata needed: simple encoding possible (less involved than Worrel/Oaknine ’03). • Timed CSP: ◦ closed timed bounds only. ◦ expressions possible rather than constant time bounds only. tr ( S 1 → S 2 { observation obs ( m ); reset r 1 ; . . . ; reset r n ; timing s 1 ≥ lb 1 ; . . . ; timing s p ≥ lb p ; } ) � Wait max { lb 1 − s 1 , . . . , lb p − s p , 0 } ; obs . m@x → S 2( update ( � c , { r 1 , . . . , r n } , x + max { lb 1 − s 1 , . . . , lb p − s p , 0 } )) . M Roggenbach: Simulating; September 2013

Tools

Current architecture 8 Current architecture Simulation T-CSP- T-CSP Hugo+ UML TA T-CSP Visualiser History Converter Simulator M Roggenbach: Simulating; September 2013

Demo 9 Demo M Roggenbach: Simulating; September 2013

Conclusion

Summary & future work 11 Summary & future work Validation of Timed UML2 Sequence Diagrams • based on a formal semantics, • through interactive visualisation. First step towards a simulation and verification framework for timed UML2. M Roggenbach: Simulating; September 2013