Short status update on DCE3 A. Wassatsch Max-Planck Semiconductor - PowerPoint PPT Presentation

Short status update on DCE3 A. Wassatsch Max-Planck Semiconductor Laboratory Munich (Germany) 13 th International Workshop on DEPFET Detectors and Applications Ringberg 12-15.06.2013 DEPFET A r c t i v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 1

status update DCE3 testchip test preparation staggered 30 µ m bond pad pitch (org. TSMC 65nm lib, recommended by IMEC) DEPFET A r c t i v e e c t o P D e t i e x l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 2

status update DCE3 testchip test preparation staggered 30 µ m bond pad pitch (org. TSMC 65nm lib, recommended by IMEC) packaging orginal planed via IMEC, but they step back after chip delivery DEPFET A r c t i v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 2

status update DCE3 testchip test preparation staggered 30 µ m bond pad pitch (org. TSMC 65nm lib, recommended by IMEC) packaging orginal planed via IMEC, but they step back after chip delivery ball-wetch bond technology needed, contact with different commercial vendors and research institutes DEPFET A r t i c v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 2

status update DCE3 testchip test preparation staggered 30 µ m bond pad pitch (org. TSMC 65nm lib, recommended by IMEC) packaging orginal planed via IMEC, but they step back after chip delivery ball-wetch bond technology needed, contact with different commercial vendors and research institutes only one company left after different tests for this job (optocap) DEPFET A r t i c v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 2

status update DCE3 testchip optocap bonding single layer bond adapter for 2 layer direct bonds DEPFET A r c t i v e e c t o P D e t i e x l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 3

status update DCE3 testchip optocap bonding single layer bond adapter for 2 layer direct bonds bond pad region for the second bond (wetch side) not coverd with poly silicium DEPFET A r c t i v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 3

status update DCE3 testchip optocap bonding single layer bond adapter for 2 layer direct bonds bond pad region for the second bond (wetch side) not coverd with poly silicium removed during layout postprocessing due to technology concern (width of the isolator path between the pads ) DEPFET A r c t i v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 3

status update DCE3 testchip optocap bonding single layer bond adapter for 2 layer direct bonds bond pad region for the second bond (wetch side) not coverd with poly silicium removed during layout postprocessing due to technology concern (width of the isolator path between the pads ) wetch bond foot of outer rows produces shorts to neigbour wires DEPFET A r t i c v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 3

status update DCE3 testchip optocap bonding single layer bond adapter for 2 layer direct bonds bond pad region for the second bond (wetch side) not coverd with poly silicium removed during layout postprocessing due to technology concern (width of the isolator path between the pads ) wetch bond foot of outer rows produces shorts to neigbour wires long wire bond to the outer side pads fixing that problem (alternative 2 layer bond adapter DEPFET A r t i c v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 3

status update DCE3 testchip test results (prelim.) up to now 6 devices fully bonded DEPFET A r c t i v e e c t o P D e t i e x l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 4

status update DCE3 testchip test results (prelim.) up to now 6 devices fully bonded JTAG on all devices work DEPFET A r c t i v e e c t o P D e t i e x l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 4

status update DCE3 testchip test results (prelim.) up to now 6 devices fully bonded JTAG on all devices work first device (board 3) has multiple substrate contacts (higher power consumtion in the io net), after fixing the bond pressure the following devices doesn’t have these error DEPFET A r c t i v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 4

status update DCE3 testchip test results (prelim.) up to now 6 devices fully bonded JTAG on all devices work first device (board 3) has multiple substrate contacts (higher power consumtion in the io net), after fixing the bond pressure the following devices doesn’t have these error all boards has shorts and/or opens in the dhp data input lines debug via the JTAG io scan cells only single step modus of the core via JTAG possible (very slow) DEPFET A r t i c v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 4

status update DCE3 testchip manpower (?) currently the dce3 is a single person project (with the exception of bonding and pcb assembly) DEPFET A r c t i v e e c t o P D e t i e x l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 5

status update DCE3 testchip manpower (?) currently the dce3 is a single person project (with the exception of bonding and pcb assembly) many different tasks and topic areas (algorithm design, hdl coding and verification, synthesis and asic layout, pcb design, firmware development for fpga and embedded µ C , software for test and slow control, ... ) DEPFET A r c t i v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 5

status update DCE3 testchip manpower (?) currently the dce3 is a single person project (with the exception of bonding and pcb assembly) many different tasks and topic areas (algorithm design, hdl coding and verification, synthesis and asic layout, pcb design, firmware development for fpga and embedded µ C , software for test and slow control, ... ) a single person can’t be an expert in all of these areas DEPFET A r c t i v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 5

status update DCE3 testchip manpower (?) currently the dce3 is a single person project (with the exception of bonding and pcb assembly) many different tasks and topic areas (algorithm design, hdl coding and verification, synthesis and asic layout, pcb design, firmware development for fpga and embedded µ C , software for test and slow control, ... ) a single person can’t be an expert in all of these areas possible tasks for collaborators DHH serial interface (hardware) ipbus communication interface for slow control (soft+hardware) test firmware development (embedded software) for further dce3 qualification .. DEPFET A r t i c v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 5

status update DCE3 testchip How to proceed further with the dce3 ? at a point, where we did not find a fix for the interconnection problem of our asic (bonds), we have to decide how we go on the working JTAG and the JTAG core test show, that the TSMC technology themselves is under control the hdl algorithm simulations, shows the functionality of the dce3 risk: speed can’t be verified due to the bonding problems, so only syn and p & r results (backanno. simu) for that submission of the full asic (5k+ nodes) with simple pad configuration (not staggered) end of the year ? option: bump pads to recover pad area for clustering agents (?) DEPFET A r t i c v e e c t o P D e t i x e l 13 th Depfet WS A. Wassatsch (MPI HLL) Short status update on DCE3 6