Section 16 Section 16 System Design a 16-1 1
Operating Modes Operating Modes a 16-2 2
Operating Modes • User mode Causes exceptions when protected resources are accessed. May be used for algorithm/application code • Supervisor mode has unprotected access to all resources. May be used for O/S kernel, device drivers, debuggers, ISRs • Emulator (or Debug) mode has supervisor abilities and is accessible via JTAG Operating Modes provide a feature to implement RTOS architectures and Multitasking schemes. Smaller applications may simply run in Supervisor mode all the time. a 16-3 3
Operating Modes Operating Modes a 16-4 4
Dynamic Power Management Dynamic Power Management a 16-5 5
Power Management Options Power Management Options • Low Active Power − Flexible power management with automatic power-down for unused peripheral sections − Dynamic Power Management allows dynamic modification of both frequency and voltage • Low Standby Power − 4 Power modes − Real Time Clock with alarm and wakeup features a 16-6 6
Dynamic Power Management Dynamic Power Management Blackfin Tahoe Power Consumption P α F * V 2 • Clocks to unused peripherals are automatically disabled. mW At specified Vdd (MHz) MHz • Integrated Switching CCLK attainable Regulator Controller mW − SW-based Voltage- Scaling Capability 0 1.2 1.1 1.0 0.9 0.8 Vdd Internal a 16-7 7
Blackfin DSPs DSPs Blackfin Control Voltage & Frequency Control Voltage & Frequency • Onboard, software-controlled switching regulator controller • Highly flexible 1x-64x PLL allows easy frequency scaling • Multiple Power-Down Modes • Functional & Peripheral Blocks are Clocked Only When Used Function Example Example MHz Vdd (V) Dynamic Power Profiling Tools F 0 (x) 550 1.1 Management Audit MIPS Using RTOS or Requirements F 1 (y) 250 0.95 Firmware By Function F n (z) 100 0.8 a 16-8 8
Blackfin DSPs DSPs Blackfin Optimize Power Consumption Optimize Power Consumption Vdd 1.1V, 550 MHz DSP Operation t 0.9V, 250 MHz PLL DSP Operation Settling 0.8V, 100 MHz PLL Regulator Settling DSP Operation Regulator Transition Power Transition Consumption Just varying the frequency mW Dynamic Power Management Varying the voltage and frequency a 16-9 9
Power Management States Mode Relative Power Notes Savings Full On Min Max performance Active Low Full core operation at CLKIN. System DMA to L1 supported. PLL is bypassed and can be disabled. Sleep High Core idle. CCLK disabled. SCLK enabled. Deep Sleep Very High Core idle. Only Real-Time Clock enabled. Exit only via HW reset or RTC interrupt. Hibernate Max VDDINT is disabled. Only VDDEXT applied. Power up via HW reset or RTC interrupt. a 16-10 10
Power Mode Transitions Power Mode Transitions a 16-11 11
Clock States in Different Power Modes Mode PLL PLL Bypassed? Core Clock System Clock (CCLK) (SCLK) Full On Enabled No Enabled Enabled Active Enabled or Yes Enabled Enabled Disabled Enabled No Disabled Enabled Sleep Deep Sleep Disabled --- Disabled Disabled Hibernate a 16-12 12
BF533 Clocking BF533 Clocking • The BF533 has 2 internal clock domains: CCLK (core clock) and SCLK (system clock) − CCLK is divided down from the PLL VCO frequency (via CSEL bits in PLL_DIV), or equals the CLKIN pin frequency if the PLL is bypassed − SCLK is divided down from the PLL VCO frequency (via SSEL bits in PLL_DIV), or equals the CLKIN pin frequency if the PLL is bypassed • SCLK must not exceed 133 MHz • CLKIN can be driven from external oscillator or crystal • Programmable PLL supports 1x to 64x frequency multiplication, enabling high-speed operation with low-frequency clock inputs − Program via bits in PLL_CTL register a 16-13 13
Phase-Locked Loop Architecture CSEL[1:0] CCLK SELECT VCO/CCLK PHASE LOOP /1 or /2 VCO CLKIN DETECT FILTER SCLK SELECT VCO/SSLK DF DIVIDER MSEL[5:0] SSEL[3:0] BYPASS a 16-14 14
CCLK Ratio Control • Upon reset, CSEL[1:0] = 00 a 16-15 15
SCLK Ratio Control SCLK Ratio Control SSEL[3:0] • Upon reset, SSEL[3:0] = 0101 a 16-16 16
PLL Control Register (PLL_CTL) PLL Control Register (PLL_CTL) • Controls operation of the PLL, specifying loop parameters and global control bits a 16-17 17
PLL Divide Register (PLL_DIV) PLL Divide Register (PLL_DIV) • Programmer must ensure SCLK frequency always less than or equal to CCLK frequency − Otherwise, SCLK will be automatically adjusted to fall into compliance, but not necessarily optimized for top allowable speed • Programmer must ensure SCLK frequency does not exceed 133 MHz a 16-18 18
Programming PLL Transitions Programming PLL Transitions • Simply modifying PLL_CTL bits will not change the PLL operating mode until a specific code sequence executes: − CLI R0; /* disable interrupts */ − IDLE; /* drain pipeline and send core into idle state */ − STI R0; /* re-enable interrupts after wakeup */ • This sequence is necessary when changes have been made to MSEL, DF, or operating state bits (PDWN, BYPASS, STOPCK) − However, changes to CSEL or SSEL divide ratios take effect immediately, without needing the above sequence • If the CLKIN-to-VCO multiplier has been changed, or the PLL has been re-enabled, the PLL will now need to relock a 16-19 19
PLL Status Register (PLL_STAT) PLL Status Register (PLL_STAT) • PLL_STAT indicates the operating mode of the PLL and the ADSP-BF533 processor a 16-20 20
Relocking the PLL Relocking the PLL • PLL lock count starts once the IDLE instruction has executed • PLL lock counter is cleared and then increments each SCLK cycle • When it reaches the value programmed into the PLL_LOCKCNT MMR, the PLL_LOCKED bit is set in PLL_STATUS • Then the PLL Wakeup interrupt is asserted, and an interrupt will occur if this interrupt is enabled in SIC_IMASK a 16-21 21
PLL Lock Count Register (PLL_LOCKCNT) PLL Lock Count Register (PLL_LOCKCNT) • PLL_LOCKCNT defines the number of SCLK cycles before the PLL_LOCKED bit (in PLL_STAT) gets set after a PLL transition • Can generate system wakeup (in SIC_IWR) when lock count reached a 16-22 22
IDLE state IDLE state • After executing ‘IDLE’, an ‘SSYNC’ instruction automatically occurs. − The DSP core stops executing instructions, retains the contents of pipeline and waits for an interrupt or wakeup. − PLL, CCLK and SCLK continue running • 2 ways to leave an IDLE state − DSP services an interrupt. DSP will return to the instruction following the IDLE after executing the RTI instruction. − A peripheral wakes the DSP up (based on SIC_IWR settings), but no interrupt occurs. DSP returns to instruction that follows IDLE a 16-23 23
System Interrupt Wakeup- -Enable Register Enable Register System Interrupt Wakeup (SIC_IWR) (SIC_IWR) • Choose the peripherals that can wake the core from an idle state in SIC_IWR a 16-24 24
On- -chip Voltage Regulation chip Voltage Regulation On When using on-chip regulator, tie both Vrout pins together •BF533/BF561 has internal switching regulator controller • NOT a linear regulator •External FET, Diode, L, C must be supplied •2.25V – 3.6V input range regulated down to VDDint (0.8V-1.2V) a 16-25 25
PLL Control Register (PLL_CTL) PLL Control Register (PLL_CTL) • Controls operation of the PLL, specifying loop parameters and global control bits a 16-26 26
ADSP- -BF533 Voltage Regulator Control Register BF533 Voltage Regulator Control Register ADSP (VR_CTL) (VR_CTL) To bypass the on-chip regulator •Leave the 2 VROUT pins floating •Set FREQ[1:0] in VR_CTL to ’00’ •Connect external 0.8V-1.2V supply to VDDint pins a 16-27 27
Resetting the ADSP- -BF533 BF533 Resetting the ADSP a 16-28 28
Reset Types System transitions into boot mode sequence upon completion of internal reset • Both of these SW resets are used primarily for debugging purposes. • The system may be in an unreliable state after a SW reset period ends. Occurs when an Therefore, execution must be from exception is L1 memory after a Core or generated while Peripheral SW Reset. another exception is being handled a 16-29 29
Hardware Reset Hardware Reset • Asynchronous • /RESET pin asserted low until after supplies have stabilized • After pin deasserted, reset timer allows all peripherals to complete a reset • Interrupt request generated • System then moves into boot mode (based on BMODE pins) a 16-30 30
Staying in Supervisor Mode after Reset Staying in Supervisor Mode after Reset • If executing from external memory after hardware reset, the ADSP-BF533 will be in the Reset ISR • This implies the part is in Supervisor mode, but… − Lower priority events can not be serviced until you return from Reset ISR − Customer can force the lowest priority interrupt in order to remain in Supervisor mode • If booting after hardware reset, the above process is automatically performed by the Boot ROM a 16-31 31
Recommend
More recommend
