RV-IOV: Tethering RISC-V Processors via Scalable I/O Virtualization - PowerPoint PPT Presentation

RV-IOV: Tethering RISC-V Processors via Scalable I/O Virtualization Luis Vega and Michael B. Taylor Bespoke Silicon Group University of Washington 1

Berkeley’s Tethered Rocket core The host system provide support for: Rocket Core • Memory subsystem • Load binaries • Start/terminate programs • System call offloading (w/ PK) Host System • Emulate peripheral devices (w/ OS) 2

Berkeley’s Rocket Emulation Platforms Zybo Zedboard ZC706 https://github.com/ucb-bar/fpga-zynq 3

Challenge #1: ASIC prototyping FC I/O Package cost ($) BGA QFP I/O I/O WL-CSP QFN I/O ~68 ~300 ~1k ~2k Total package I/O I/O Host Mem Total Total Package I/O ~~ 3 x Data-I/O # 36 298 334 (power supply reasons) 4

Challenge #2: FPGA (LUT) resources 5

Solution: RV-IOV • RV-IOV decouples the Rocket core from the host processor • RV-IOV allows multiple Rocket cores to be implemented on external ASIC prototypes or FPGA emulation boards • RV-IOV extends Rocket supported FPGA boards 6

RV-IOV system level Host (FPGA) Client (FPGA or ASIC) Scalable Host Processor Rocket Rocket system system Virtual I/O (1) (n) Arbiter RV-IOV RV-IOV RV-IOV RV-IOV Switch Switch Physical I/O Shared interconnect 7

RV-IOV - internal operations Rocket core Host Mem 1. Memory serialization 2. Stream interleaving RV-IOV single stream 8

RV-IOV - memory serialization Rocket core Mem host {aw, w, b} {ar, r} • AXI4 memory protocol is serialized write read • Merge write/read memory channels into a single Memory bidirectional channel serializer memory host 9

RV-IOV - stream interleaving memory host • Interleave memory and host packets • Round robin fashion Stream • Flow control: credit protocol Interleaving • Maximize throughput • Avoid deadlocks single stream 10

RV-IOV FPGA evaluation Zedboard DoubleTrouble DoubleTrouble is an Open Source Emulation Platform https://bjump.org 11

RV-IOV FPGA evaluation One hop system Two hop system 12

Rocket core configuration • 5 stage, in-order, scalar processor • Double precision, floating point • I-cache: 16 KB 4-way assoc. • D-cache: 16 KB 4-way assoc. • RV64G ISA 13

Results 14

Conclusion • RV-IOV increases implementation flexibility for both ASIC and FPGA Rocket designs • RV-IOV allows larger Rocket core configurations, i.e. multi- core and powerful accelerators • RV-IOV will be available @ https://bjump.org/rv_iov 15

Questions? 16