Routing Information Protocol (RIP) Modeled in UML using I-Logixs - PowerPoint PPT Presentation

Routing Information Protocol (RIP) Modeled in UML using I-Logix’s Rhapsody IPS Project, March 2006 Presented by: Masood Khosroshahy B E G I N N I N G 1

Introduction • The Routing Information Protocol (RIP) is one of the family of IP Routing protocols, and is an Interior Gateway Protocol (IGP) designed to distribute routing information within an Autonomous System (AS). • RIP is a vector routing protocol, according to which the routers exchange network reachability information with their nearest neighbors. • In other words, the routers communicate to each other the sets of destinations that they can reach, and the next hop address to which data should be sent in order to reach those destinations. 2

Introduction …continued • Periodically, each router advertises the entire contents of its routing table over all of its interfaces. • Whenever a RIP router receives such an advertisement, it puts all of the appropriate routes into its routing table and begins using it to forward packets. This process ensures that every network connected to every router eventually becomes known to all routers. • Every route has a property called Cost , which indicates the "distance" to the route's destination. • The maximum Cost, or metric, permitted by RIP is 16, which means that a route is unreachable. 3

Some of the optimizations of its basic algorithm • When a router detects a change to its routing table, it sends an immediate "triggered" update. This speeds up stabilization of the routing table and elimination of routing loops. • When router A has learnt a route from router B, it does NOT advertise the route back to B. This ensures that B is never under the impression that A has a different way of getting to the same destination. This technique is known as “ split horizon ”. 4

Structure Diagram Network 1 r4:Router 1 scheduler:Scheduler numberOfInitializ... iSchedulerRouter3 iSchedulerRouter3 neighbours:Nei... pTimerIn pTimerIn replyTo:pRouter_CPtr pScheduler pScheduler ripMessageSendingIteration:int pTimerOut pTimerOut send_RIPtable():... evRIP():void setReplyTo(p:void *):void sendingTimerToAll():void pRIP1 pRIP1 pRIP2 pRIP3 pRIP3 pRIP4 pRIP4 pRIP2 iRouterScheduler1 iRouterScheduler1 pRouter1 pRouter1 pRouter4 pRouter4 pRouter2 pRouter2 pRouter3 pRouter3 iRouterScheduler1 iRouterScheduler1 iRouterScheduler1 iRouterScheduler1 iRouterScheduler1 iRouterScheduler1 iRouterScheduler1 iRouterScheduler1 iSchedulerRouter3 iSchedulerRouter3 iSchedulerRouter3 iSchedulerRouter3 iSchedulerRouter3 iSchedulerRouter3 iSchedulerRouter3 iSchedulerRouter3 pRIP4 pRIP4 pRIP1 pRIP1 pRIP1 pRIP1 pRIP3 pRIP3 pRIP2 pRIP2 pRIP4 pRIP4 pRIP3 pRIP3 pRIP4 pRIP4 pRIP1 pRIP1 pRIP2 pRIP2 1 r3:Router pRIP2 pRIP2 1 r1:Router 1 r2:Router pRIP3 pRIP3 iSchedulerRouter3 iSchedulerRouter3 numberOfInitializatio... pScheduler pScheduler numberOfInitiali... numberOfInitializ... neighbours:Neighbo... neighbours:Nei... neighbours:Neig... send_RIPtable():void send_RIPtable()... send_RIPtable():v... evRIP():void evRIP():void evRIP():void iRouterScheduler1 iRouterScheduler1 pScheduler pScheduler pScheduler pScheduler iSchedulerRouter3 iSchedulerRouter3 iRouterScheduler1 iRouterScheduler1 iSchedulerRouter3 iSchedulerRouter3 iRouterScheduler1 iRouterScheduler1 5

Statechart of Scheduler Initial values: mainState ripMessageSendin time = 15 /ripMessageSendingIteration++; /ripMessageSendingIteration++; /ripMessageSendingIteration++; time = ripMessageSendingIteration*15; time = ripMessageSendingIteration*15; time = ripMessageSendingIteration*15; InitializingState evTimerSent InitialTimerState Exit Exit Wait_41_Down Wait_32_Down tm(time )/ tm(time )/ tm(time )/ if ( (time)%30 == 0 ) if ( (time)%30 == 0 ) if ( (time)%30 == 0 ) Wait_42_down sendingTimerToAll(); sendingTimerToAll(); sendingTimerToAll(); Wait_32_Down Wait_41_Down evTimer[IS_PORT(pTimerIn)]/ evTimer[IS_PORT(pTimerIn)]/ evTimer[IS_PORT(pTimerIn)]/ OUT_PORT(pRouter2)->GEN(evTopology(1,3,-4)); OUT_PORT(pRouter2)->GEN(evTopology(1,3,-4)); OUT_PORT(pRouter2)->GEN(evTopology(1,3,-4)); [time == 75]/ [time == 75]/ [time == 75]/ evTimer[IS_PORT(pTimerIn)]/ evTimer[IS_PORT(pTimerIn)]/ evTimer[IS_PORT(pTimerIn)]/ OUT_PORT(pTimerOut)->GEN(evTimer(time)); OUT_PORT(pTimerOut)->GEN(evTimer(time)); OUT_PORT(pTimerOut)->GEN(evTimer(time)); OUT_PORT(pRouter2)->GEN(evTopology(1,-4,-3)); OUT_PORT(pRouter2)->GEN(evTopology(1,-4,-3)); OUT_PORT(pRouter2)->GEN(evTopology(1,-4,-3)); TopologyToR2_42 evTimer[IS_PORT(pTimerIn)]/ evTimer[IS_PORT(pTimerIn)]/ evTimer[IS_PORT(pTimerIn)]/ tm(time +1)/ tm(time +1)/ tm(time +1)/ NewTopologyAt75 OUT_PORT(pRouter1)->GEN(evTopology(2,-4,0)); OUT_PORT(pRouter1)->GEN(evTopology(2,-4,0)); OUT_PORT(pRouter1)->GEN(evTopology(2,-4,0)); sendingTimerToAll(); sendingTimerToAll(); sendingTimerToAll(); TopologyToR2_32 TopologyToR1_41 [time == 135]/ [time == 135]/ [time == 135]/ /OUT_PORT(pRouter4)->GEN(evTopology(1,-2,0)); /OUT_PORT(pRouter4)->GEN(evTopology(1,-2,0)); /OUT_PORT(pRouter4)->GEN(evTopology(1,-2,0)); OUT_PORT(pTimerOut)->GEN(evTimer(time)); OUT_PORT(pTimerOut)->GEN(evTimer(time)); OUT_PORT(pTimerOut)->GEN(evTimer(time)); /OUT_PORT(pRouter3)->GEN(evTopology(-2,0,0)); /OUT_PORT(pRouter3)->GEN(evTopology(-2,0,0)); /OUT_PORT(pRouter3)->GEN(evTopology(-2,0,0)); tm(time +1)/ tm(time +1)/ tm(time +1)/ NewTopologyAt135 /OUT_PORT(pRouter4)->GEN(evTopology(-1,-2,0)); /OUT_PORT(pRouter4)->GEN(evTopology(-1,-2,0)); /OUT_PORT(pRouter4)->GEN(evTopology(-1,-2,0)); sendingTimerToAll(); sendingTimerToAll(); sendingTimerToAll(); TopologyToR3_32 TopologyToR4_42 [time == 195]/ [time == 195]/ [time == 195]/ TopologyToR4_41 OUT_PORT(pTimerOut)->GEN(evTimer(time)); OUT_PORT(pTimerOut)->GEN(evTimer(time)); OUT_PORT(pTimerOut)->GEN(evTimer(time)); tm(time +1)/ tm(time +1)/ tm(time +1)/ NewTopologyAt195 sendingTimerToAll(); sendingTimerToAll(); sendingTimerToAll(); Wait_41_Down Wait_32_Down 6

Sub-Statechart of State InitializingState in Scheduler InitializingState Initial Topology /OUT_PORT (pRouter1)->GEN(evT opology(2,4,0)); /OUT_PORT (pRouter1)->GEN(evT opology(2,4,0)); /OUT_PORT (pRouter1)->GEN(evT opology(2,4,0)); /OUT_PORT (pRouter1)->GEN(evT opology(2,4,0)); /OUT_PORT (pRouter1)->GEN(evInit(1)); /OUT_PORT (pRouter1)->GEN(evInit(1)); evRep_Init[IS_PORT (pRouter1)] evRep_Init[IS_PORT (pRouter1)] evRep_Init[IS_PORT (pRouter1)] evRep_Init[IS_PORT (pRouter1)] SendingToR1 TopologyToR1 Ack1 IDSentT oR1 /OUT_PORT (pRouter2)->GEN(evInit(2)); /OUT_PORT (pRouter2)->GEN(evInit(2)); /OUT_PORT (pRouter2)->GEN(evT opology(1,3,4)); /OUT_PORT (pRouter2)->GEN(evT opology(1,3,4)); /OUT_PORT (pRouter2)->GEN(evT opology(1,3,4)); /OUT_PORT (pRouter2)->GEN(evT opology(1,3,4)); evRep_Init[IS_PORT (pRouter2)] evRep_Init[IS_PORT (pRouter2)] evRep_Init[IS_PORT (pRouter2)] evRep_Init[IS_PORT (pRouter2)] IDSentT oR2 TopologyToR2 Ack2 SendingToR2 Exit Exit /OUT_PORT (pRouter3)->GEN(evInit(3)); /OUT_PORT (pRouter3)->GEN(evInit(3)); AllAckReceived /OUT_PORT (pRouter3)->GEN(evT opology(2,0,0)); /OUT_PORT (pRouter3)->GEN(evT opology(2,0,0)); /OUT_PORT (pRouter3)->GEN(evT opology(2,0,0)); /OUT_PORT (pRouter3)->GEN(evT opology(2,0,0)); IDSentT oR3 evRep_Init[IS_PORT (pRouter3)] evRep_Init[IS_PORT (pRouter3)] evRep_Init[IS_PORT (pRouter3)] evRep_Init[IS_PORT (pRouter3)] TopologyToR3 Ack3 SendingToR3 /OUT_PORT (pRouter4)->GEN(evInit(4)); /OUT_PORT (pRouter4)->GEN(evInit(4)); IDSentT oR4 /OUT_PORT (pRouter4)->GEN(evT opology(1,2,0)); /OUT_PORT (pRouter4)->GEN(evT opology(1,2,0)); /OUT_PORT (pRouter4)->GEN(evT opology(1,2,0)); /OUT_PORT (pRouter4)->GEN(evT opology(1,2,0)); evRep_Init[IS_PORT (pRouter4)] evRep_Init[IS_PORT (pRouter4)] evRep_Init[IS_PORT (pRouter4)] evRep_Init[IS_PORT (pRouter4)] Ack4 TopologyTo4 SendingToR4 7