Registers, Finite State Machines CSE 140: Components and Design - PowerPoint PPT Presentation

Lecture 7: Sequential Networks: Registers, Finite State Machines CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering 1 University of California, San Diego

D Flip-Flop (Delay) Id D Q(t) Q(t+1) Q D 0 0 0 0 1 0 1 0 CLK Q’ 2 1 0 1 3 1 1 1 State table Characteristic Expression PS D 0 1 Q(t+1) = D(t) 0 0 1 What does the equation mean? 1 0 1 NS= Q(t+1) 2

iClicker How long does a D-flip flop store a bit before its output can potentially change? A. Half a clock cycle B. One clock cycle C. Two clock cycles D. There is no minimum time 3

Rising vs. Falling Edge D Flip-Flop ’ ’ D Q D Q Internal design: The triangle Just invert servant Q Q means clock clock rather than input, edge master triggered Symbol for rising-edge Symbol for falling-edge triggered D flip-flop triggered D flip-flop rising edges falling edges Clk Clk 4

Enabled D-FFs • Inputs: CLK , D , EN – The enable input ( EN ) controls when new data ( D ) is stored • Function – EN = 1: D passes through to Q on the clock edge – EN = 0: the flip-flop retains its previous state Internal Circuit Symbol EN CLK 0 D Q Q D Q D 1 EN

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Bit Storage Overview SR latch Level-sensitive SR latch D latch D flip-flop S (set) S D S1 S D latch D latch Q ’ D Qs’ DmQm Ds C C Q C m Cs Qs Q Q Q master servant R Clk R R1 R (reset) SR can’t be 11 if D is S=1 sets Q to 1, S and R only have effect Only loads D value present at R=1 resets Q to 0. when C=1. We can stable before and while rising clock edge, so values can’t propagate to other flip - Problem: SR=11 design outside circuit so C=1, and will be 11 for only yield undefined Q. SR=11 never happens a brief glitch even if D flops during same clock cycle. when C=1. Problem: changes while C=1. Tradeoff: uses more gates avoiding SR=11 can be a Problem: C=1 too long internally than D latch, and burden. propagates new values requires more external gates than SR – but gate count is through too many latches: too short may not enable a less of an issue today. store. 7

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Shift register • Holds & shifts samples of input OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q IN CLK 9

Pattern Recognizer • Combinational function of input samples OUT OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q IN CLK 10

Counters • Sequences through a fixed set of patterns OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q IN CLK 11

What we will learn: 1. Describe the desired behavior of a sequential circuit over time (FSMs) 2. Given the behavior of a sequential circuit, implement the circuit Describing Wall-E Wall-E is a Finite State Machine Inactive Active 12 Implementing Wall-E

Finite State Machines: Describing circuit behavior over time Symbol/ Circuit 2 bit Counter 13

Finite State Machines: Describing circuit behavior over time Output over time Symbol/ Circuit CLK time Free running 2 bit Counter Q 1 Q 0 What is the expected output of the counter over time? 14

Finite State Machines: Describing circuit behavior over time Diagram that depicts Symbol/ Circuit behavior over time 00 2 bit Counter 01 11 10 15

State: What is it ? Why do we need it? Symbol/ Circuit Behavior over time CLK 2 bit Counter t 1 time t 2 PI Q: At time t 1 , what information is needed to produce the output of the counter at the next rising edge of the clock (i.e t 2 )? A. All the outputs of the counter until t 1 B. The initial output of the counter at time t=0 C. The output of the counter at current time t 1 D. We cannot determine the output of the counter at t 2 prior to t 2 16

Implementing the 2 bit counter S 0 Current state Next State S 0 S 1 S 1 S 2 S 3 S 1 S 2 S 3 S 3 S 0 S 2 Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) State Diagram State Table 17

State Table PI Q: Which of the following is the likely structure of the circuit realization of the Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) counter 0 0 0 1 A. 0 1 1 0 Combinational 1 0 1 1 circuit 1 1 0 0 Circuit with no flip flops Q B. C. D Q’ Q 0 (t) Q Combinational Q Q 0 (t) circuit D Combinational Q’ Q Q 1 (t) circuit D Q’ CLK Q 1 (t) CLK Circuit with 2 flip flops 18 Circuit with one flip flop

State Table Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) To design the combinational 0 0 0 1 circuit we need a truth table 0 1 1 0 1 0 1 1 1 1 0 0 Q B. D Q’ Q 0 (t) Combinational Q circuit D Q 1 (t) Q’ CLK D 0 (t) = Q 0 (t)’ D 1 (t) = Q 0 (t) Q 1 (t)’ + Q 0 (t)’ Q 1 (t) Circuit with 2 flip flops 19

Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) Q 0 (t+1) = Q 0 (t)’ 0 0 0 1 Q 1 (t+1) = Q 0 (t) Q 1 (t)’ + Q 0 (t)’ Q 1 (t) 0 1 1 0 1 0 1 1 1 1 0 0 State Table Q We store the current state using D-flip D Q’ flops so that: Q 0 (t) • Inputs to the combinational circuit Q don’t change while the next output is D Q’ being computed Q 1 (t) • The transition to the next state only CLK occurs at the rising edge of the clock Implementation of 2-bit counter 20

Generalized Model of Sequential Circuits Y X S(t) CLK 21

Canonical Form: Mealy and Moore Machines Mealy Machine: y i (t) = f i (X(t), S(t)) Moore Machine: y i (t) = f i (S(t)) s i (t+1) = g i (X(t), S(t)) x(t) x(t) y(t) y(t) C1 C2 C1 C2 CLK CLK S(t) S(t) Moore Machine Mealy Machine 22