Register Allocation Akim Demaille tienne Renault Roland Levillain - PowerPoint PPT Presentation

Spilling Not enough registers t1 := t1 + t2 So use the stack [sp + 4] := [sp + 4] + [sp + 8] But use temporaries to do so! t12 := [sp + 4] t13 := [sp + 8] t12 := t12 + t13 [sp + 4] := t12 Why should it solve the problem? A. Demaille, E. Renault, R. Levillain Register Allocation 33 / 98

Register Allocation with Spills Potential Actual Build Simplify Select spill spill Rebuild the graph if there were any actual spills spill when one cannot simplify, the (uses of the) temporary must be rewritten using the stack. rebuild but then, the conflict graph is to be rewritten [Appel, 1998, Matz, 2003] A. Demaille, E. Renault, R. Levillain Register Allocation 34 / 98

Yes, But Who Should be Spilled? The simplification order does not matter The spilling order matters Spilling decreases the degree of the neighbors . . . hence it enables additional simplifications . . . so “first spilled, last served” . . . therefore: spill cheap temporaries few def/uses pay attention to loops A. Demaille, E. Renault, R. Levillain Register Allocation 35 / 98

Yes, But Who Should be Spilled? The simplification order does not matter The spilling order matters Spilling decreases the degree of the neighbors . . . hence it enables additional simplifications . . . so “first spilled, last served” . . . therefore: spill cheap temporaries few def/uses pay attention to loops A. Demaille, E. Renault, R. Levillain Register Allocation 35 / 98

Yes, But Who Should be Spilled? The simplification order does not matter The spilling order matters Spilling decreases the degree of the neighbors . . . hence it enables additional simplifications . . . so “first spilled, last served” . . . therefore: spill cheap temporaries few def/uses pay attention to loops A. Demaille, E. Renault, R. Levillain Register Allocation 35 / 98

Yes, But Who Should be Spilled? The simplification order does not matter The spilling order matters Spilling decreases the degree of the neighbors . . . hence it enables additional simplifications . . . so “first spilled, last served” . . . therefore: spill cheap temporaries few def/uses pay attention to loops A. Demaille, E. Renault, R. Levillain Register Allocation 35 / 98

Yes, But Who Should be Spilled? The simplification order does not matter The spilling order matters Spilling decreases the degree of the neighbors . . . hence it enables additional simplifications . . . so “first spilled, last served” . . . therefore: spill cheap temporaries few def/uses pay attention to loops A. Demaille, E. Renault, R. Levillain Register Allocation 35 / 98

Yes, But Who Should be Spilled? The simplification order does not matter The spilling order matters Spilling decreases the degree of the neighbors . . . hence it enables additional simplifications . . . so “first spilled, last served” . . . therefore: spill cheap temporaries few def/uses pay attention to loops A. Demaille, E. Renault, R. Levillain Register Allocation 35 / 98

Yes, But Who Should be Spilled? The simplification order does not matter The spilling order matters Spilling decreases the degree of the neighbors . . . hence it enables additional simplifications . . . so “first spilled, last served” . . . therefore: spill cheap temporaries few def/uses pay attention to loops A. Demaille, E. Renault, R. Levillain Register Allocation 35 / 98

Yes, But Who Should be Spilled? The simplification order does not matter The spilling order matters Spilling decreases the degree of the neighbors . . . hence it enables additional simplifications . . . so “first spilled, last served” . . . therefore: spill cheap temporaries few def/uses pay attention to loops A. Demaille, E. Renault, R. Levillain Register Allocation 35 / 98

Optimistic Coloring We miss many opportunities to avoid the stack a d b c Handle spills as if they were simplified ( potential spills ) then try to color them There might not be actual spills A. Demaille, E. Renault, R. Levillain Register Allocation 36 / 98

Optimistic Coloring We miss many opportunities to avoid the stack a d b c Handle spills as if they were simplified ( potential spills ) then try to color them There might not be actual spills A. Demaille, E. Renault, R. Levillain Register Allocation 36 / 98

Optimistic Coloring We miss many opportunities to avoid the stack a d b c Handle spills as if they were simplified ( potential spills ) then try to color them There might not be actual spills A. Demaille, E. Renault, R. Levillain Register Allocation 36 / 98

Optimistic Coloring We miss many opportunities to avoid the stack a d b c Handle spills as if they were simplified ( potential spills ) then try to color them There might not be actual spills A. Demaille, E. Renault, R. Levillain Register Allocation 36 / 98

Coalescing Interference Graph 1 Coloring by Simplification 2 Spilling Coalescing Precolored Nodes Implementation Alternatives to Graph Coloring 3 A. Demaille, E. Renault, R. Levillain Register Allocation 37 / 98

Coalescing Some low-level form of copy propagation While building traces we tried to remove jump s While allocating registers, we try to remove move s live-in : t2 t1 := ... t2 := t1 + t2 t3 := t2 t4 := t1 + t3 t2 := t3 + t4 t1 := t2 - t4 live-out : t1 A. Demaille, E. Renault, R. Levillain Register Allocation 38 / 98

Coalescing Some low-level form of copy propagation While building traces we tried to remove jump s While allocating registers, we try to remove move s live-in : t2 t1 := ... t2 := t1 + t2 t3 := t2 t4 := t1 + t3 t2 := t3 + t4 t1 := t2 - t4 live-out : t1 A. Demaille, E. Renault, R. Levillain Register Allocation 38 / 98

Coalescing Some low-level form of copy propagation While building traces we tried to remove jump s While allocating registers, we try to remove move s live-in : t2 t1 := ... t2 := t1 + t2 t3 := t2 t4 := t1 + t3 t2 := t3 + t4 t1 := t2 - t4 live-out : t1 A. Demaille, E. Renault, R. Levillain Register Allocation 38 / 98

Coalescing Improves the Coloralibility t1 t2 t3 t4 A. Demaille, E. Renault, R. Levillain Register Allocation 39 / 98

Coalescing Improves the Coloralibility t1 t1 t2 t2&t3 t3 t4 t4 A. Demaille, E. Renault, R. Levillain Register Allocation 39 / 98

Coalescing Improves the Coloralibility t1 t1 t2 t2&t3 t3 t4 t4 t1 and t4 have one neighbor less! A. Demaille, E. Renault, R. Levillain Register Allocation 39 / 98

Yes, But Coalesce Who? Conservative Coalescing : don’t make it harder. Coalesce a and b if Briggs ab has fewer than k neighbors of significant degree. George every neighbor of a is of insignificant degree already interfering with b George’s criterion is well suited for real registers A. Demaille, E. Renault, R. Levillain Register Allocation 40 / 98

Yes, But Coalesce Who? Conservative Coalescing : don’t make it harder. Coalesce a and b if Briggs ab has fewer than k neighbors of significant degree. George every neighbor of a is of insignificant degree already interfering with b George’s criterion is well suited for real registers A. Demaille, E. Renault, R. Levillain Register Allocation 40 / 98

Yes, But Coalesce Who? Conservative Coalescing : don’t make it harder. Coalesce a and b if Briggs ab has fewer than k neighbors of significant degree. George every neighbor of a is of insignificant degree already interfering with b George’s criterion is well suited for real registers A. Demaille, E. Renault, R. Levillain Register Allocation 40 / 98

Yes, But Coalesce Who? Conservative Coalescing : don’t make it harder. Coalesce a and b if Briggs ab has fewer than k neighbors of significant degree. George every neighbor of a is of insignificant degree already interfering with b George’s criterion is well suited for real registers A. Demaille, E. Renault, R. Levillain Register Allocation 40 / 98

Yes, But Coalesce Who? Conservative Coalescing : don’t make it harder. Coalesce a and b if Briggs ab has fewer than k neighbors of significant degree. George every neighbor of a is of insignificant degree already interfering with b George’s criterion is well suited for real registers A. Demaille, E. Renault, R. Levillain Register Allocation 40 / 98

Yes, But Coalesce Who? Conservative Coalescing : don’t make it harder. Coalesce a and b if Briggs ab has fewer than k neighbors of significant degree. George every neighbor of a is of insignificant degree already interfering with b George’s criterion is well suited for real registers A. Demaille, E. Renault, R. Levillain Register Allocation 40 / 98

Yes, But Coalesce Who? Conservative Coalescing : don’t make it harder. Coalesce a and b if Briggs ab has fewer than k neighbors of significant degree. George every neighbor of a is of insignificant degree already interfering with b George’s criterion is well suited for real registers A. Demaille, E. Renault, R. Levillain Register Allocation 40 / 98

Interference Graph [Appel, 1998] b Four registers: r1 , r2 , r3 , r4 . live in: k j g := [j + 12] g e c h := k - 1 f := g * h e := [j + 8] m := [j + 16] h f d b := [f] c := e + 8 d := c j m k := m + 4 j := b live out: d k j k A. Demaille, E. Renault, R. Levillain Register Allocation 41 / 98

Interference Graph: Simplify 0 b g e c h f d j m g k A. Demaille, E. Renault, R. Levillain Register Allocation 42 / 98

Interference Graph: Simplify 1 b g e c h f d h j m g k A. Demaille, E. Renault, R. Levillain Register Allocation 43 / 98

Interference Graph: Simplify 2 b g e c h f d k h j m g k A. Demaille, E. Renault, R. Levillain Register Allocation 44 / 98

Interference Graph: Simplify 3 c&d b e g c & d f h k h m j g k A. Demaille, E. Renault, R. Levillain Register Allocation 45 / 98

Interference Graph: Simplify 4 c&d j&b g e j & b c & d k h k h f g m A. Demaille, E. Renault, R. Levillain Register Allocation 46 / 98

Interference Graph: Simplify 5 c&d j&b c&d g e j & b c & d k h k h f g m A. Demaille, E. Renault, R. Levillain Register Allocation 47 / 98

Interference Graph: Simplify 6 c&d j&b j&b c&d g e j & b c & d k h k h f g m A. Demaille, E. Renault, R. Levillain Register Allocation 48 / 98

Interference Graph: Simplify 7 c&d j&b f j&b c&d g e j & b c & d k h k h f g m A. Demaille, E. Renault, R. Levillain Register Allocation 49 / 98

Interference Graph: Simplify 8 c&d m j&b f j&b c&d g e j & b c & d k h k h f g m A. Demaille, E. Renault, R. Levillain Register Allocation 50 / 98

Interference Graph: Simplify 9 c&d e m j&b f j&b c&d g e j & b c & d k h k h f g m A. Demaille, E. Renault, R. Levillain Register Allocation 51 / 98

Interference Graph: Simplify 9 c&d e m j&b f j&b c&d g e:1 j & b c & d k h k h f g m A. Demaille, E. Renault, R. Levillain Register Allocation 52 / 98

Interference Graph: Simplify 8 c&d m j&b f j&b c&d g e:1 j & b c & d k h k h f g m:2 A. Demaille, E. Renault, R. Levillain Register Allocation 53 / 98

Interference Graph: Simplify 7 c&d j&b f j&b c&d g e:1 j & b c & d k h k h f:3 g m:2 A. Demaille, E. Renault, R. Levillain Register Allocation 54 / 98

Interference Graph: Simplify 6 c&d j&b:4 j&b c&d g e:1 j & b c & d k h k h f:3 g m:2 A. Demaille, E. Renault, R. Levillain Register Allocation 55 / 98

Interference Graph: Simplify 5 c&d:1 j&b:4 c&d g e:1 j & b c & d k h k h f:3 g m:2 A. Demaille, E. Renault, R. Levillain Register Allocation 56 / 98

Interference Graph: Simplify 4 c&d:1 b:4 e:1 g j & b c & d f:3 h k h m:2 j:4 g k A. Demaille, E. Renault, R. Levillain Register Allocation 57 / 98

Interference Graph: Simplify 3 b:4 g e:1 c:1 h f:3 d:1 c & d k h j:4 m:2 g k A. Demaille, E. Renault, R. Levillain Register Allocation 58 / 98

Interference Graph: Simplify 2 b:4 g e:1 c:1 h f:3 d:1 k h j:4 m:2 g k:2 A. Demaille, E. Renault, R. Levillain Register Allocation 59 / 98

Interference Graph: Simplify 1 b:4 g e:1 c:1 h:2 f:3 d:1 h j:4 m:2 g k:2 A. Demaille, E. Renault, R. Levillain Register Allocation 60 / 98

Interference Graph: Simplify 0 b:4 g:1 e:1 c:1 h:2 f:3 d:1 j:4 m:2 g k:2 A. Demaille, E. Renault, R. Levillain Register Allocation 61 / 98

Interference Graph: Result live in: k j live in: r2 r4 g := [j + 12] r1 := [r4 + 12] h := k - 1 r2 := r2 - 1 f := g * h r3 := r1 * r2 e := [j + 8] r1 := [r4 + 8] m := [j + 16] r2 := [r4 + 16] b := [f] r4 := [r3] c := e + 8 r1 := r1 + 8 d := c # r1 := r1 k := m + 4 r2 := r2 + 4 j := b # r4 := r4 live out: d k j live out: r1 r2 r4 A. Demaille, E. Renault, R. Levillain Register Allocation 62 / 98

Precolored Nodes Interference Graph 1 Coloring by Simplification 2 Spilling Coalescing Precolored Nodes Implementation Alternatives to Graph Coloring 3 A. Demaille, E. Renault, R. Levillain Register Allocation 63 / 98

Hard Registers Some nodes are precolored: the real registers the stack pointer ( $sp ) the frame pointer ( $fp ) the argument registers ( $a0 , $a1 , etc.) the return value ( $v0 , $v1 ) the return address ( $ra ) etc. They all interfere with each other They cannot be simplified (infinite degree) A. Demaille, E. Renault, R. Levillain Register Allocation 64 / 98

Hard Registers Some nodes are precolored: the real registers the stack pointer ( $sp ) the frame pointer ( $fp ) the argument registers ( $a0 , $a1 , etc.) the return value ( $v0 , $v1 ) the return address ( $ra ) etc. They all interfere with each other They cannot be simplified (infinite degree) A. Demaille, E. Renault, R. Levillain Register Allocation 64 / 98

Hard Registers Some nodes are precolored: the real registers the stack pointer ( $sp ) the frame pointer ( $fp ) the argument registers ( $a0 , $a1 , etc.) the return value ( $v0 , $v1 ) the return address ( $ra ) etc. They all interfere with each other They cannot be simplified (infinite degree) A. Demaille, E. Renault, R. Levillain Register Allocation 64 / 98