Ramping New Products Yields Ramping New Products Yields in the Deep Submicron Submicron Age Age in the Deep ISQED 2000 March 21st, 2000 PDF Solutions, Inc. John K. Kibarian 21-Mar-00 • 1 • PDF Solutions, Inc.
Major Points Major Points G Increasing design and process complexity becoming critical factor leading to yield loss G Systematic yield loss component is significant, growing, and recoverable G Fundamental new approach, focused on integration between design, process and manufacturing, is required to recover yield loss 21-Mar-00 • 2 • PDF Solutions, Inc.
Outline Outline G Product Yield Ramps: the market pressures G The Design-Manufacturing Integration Problem G Solution G Examples G Concluding remarks 21-Mar-00 • 3 • PDF Solutions, Inc.
Complexity is Increasing Across the Board Complexity is Increasing Across the Board IC Complexity: Transistors 1,000 Transistors (M) IP Reuse is IP Reuse is 100 Critical to Get Critical to Get Designs to Market Designs to Market 10 Faster Faster 1 1997 1999 2001 2003 2005 2008 IC Complexity: Processing Steps 600 Unless Corrected, Unless Corrected, Processing Steps 500 Increased Processing Increased Processing 400 300 Complexity Reduces Complexity Reduces 200 Yield up to 5% per Year Yield up to 5% per Year 100 0 1997 1999 2002 2005 2008 21-Mar-00 • 4 • PDF Solutions, Inc.
The Window is Tightening The Window is Tightening Years to 1 Million Sales 3 Color TV Cable TV VCR Cellular PCS PC B&W TV The demand is The demand is Sales Playstation II 2 Volume DVD accelerating accelerating 1 Million 1 Units 0 5 10 15 20 25 5 10 15 20 Design Rules: 0.13u 0.18u 0.25u 0.35u 0.5u 5000 0.8u 4000 Wafers per Week There is less time There is less time 3000 to bring up the to bring up the 2000 volume volume Accelerating Ramp Rates 1000 0 0 12 24 36 Months to Full Production 21-Mar-00 • 5 • PDF Solutions, Inc. Sources: 1) D. Merriman, “Wireless Comm. Report”, BIS, Boston, 1995+Dataquest 2) IC Insights/Ross Assoc.
Missing the Window is Expensive Missing the Window is Expensive Annual COGS Savings per 10,000 Three costs: Three costs: Wafers 1 $200m • Lost market share • Lost market share • Increased NRE Increased NRE • $100m • Increased Costs of • Increased Costs of $0m Goods Sold (COGS) Goods Sold (COGS) Top 25% Top 5% Integration effects market entry point, Integration effects market entry point, performance, and cost basis performance, and cost basis 21-Mar-00 • 6 • PDF Solutions, Inc.
And Those Yield Loss $$$ are Recoverable ... And Those Yield Loss $$$ are Recoverable ... Yield Loss Components 100% Bad News: Bad News: 75% Integration Issues Integration Issues 50% Now Account for 30% Now Account for 30% 25% of Yield Loss During of Yield Loss During 0% Ramp Ramp Mature (.35um) Advanced (.18um) Design Manufacturing Integration Contamination Materials+Other Process Variation Recoverable Yield Loss 100% Good News: Good News: 75% Nearly All Integration Nearly All Integration 50% Related Loss is Related Loss is 25% Recoverable Recoverable 0% Mature (.35um) Advanced (.18um) Design Manufacturing Integration Contamination Materials+Other Process Variation 21-Mar-00 • 7 • PDF Solutions, Inc.
… but, an Integrated Approach is Required … but, an Integrated Approach is Required Traditional Holistic Traditional Holistic Design Design Design Design Design Design Process Process Process Process Integrated Process Process Solution Manufacturing Manufacturing Manufacturing Manufacturing Manufacturing Manufacturing Isolated Approach “ Ask yourself this: Why does a MIPS core cost 25 cents, and you go to QED and there's a 100-fold increase in value? … the QED part is worth $25 because it is implemented in silicon.” — Rob Chaplinsky, general partner of Mohr Davidow Ventures — 21-Mar-00 • 8 • PDF Solutions, Inc.
Technical Issues Have Both Design and Technical Issues Have Both Design and Manufacturing Implications Manufacturing Implications New Technology Impact on Design / Compensation Design – Manufacturing Manufacturing Issue Interface • ILD Variability • Dummy fill • What is the circuit Chemical • Depth of focus • Increased design Mechanical performance impact? • What is the optimal • Capacitance Polishing (CMP) margin dummy fill strategy? variability I-Line @ 0.35 µ m • Large w/in chip line • Optical Proximity • Printability verification DuV @ 0.25 µ m and width variation Correction after OPC? • Gap fill issues? below • Increased relative • Statistical design • Traditional worst case Channel & Source • Increase margins Drain Engineering variability of corners not valid transistor RTA, Tox, Poly CD performance • Debugging product • Black box yield • Fault localization Re-use of large design cores yield issues models difficult 21-Mar-00 • 9 • PDF Solutions, Inc.
Design or Manufacturing Problem? Design or Manufacturing Problem? Both! Both! CMP causes layout dependent Dummy fill improves uniformity But capacitance can go up! dielectric variation which causes yield loss C B C A C A C D C B Dielectric thickness (um) (b) C C Die X (mm) Die X (mm) Die Y (mm) Die Y (mm) B. Stine et al, Transactions on Electron Devices, Vol 45 No. 3 Optimal solution depends on both design and process considerations 21-Mar-00 • 10 • PDF Solutions, Inc.
Simulating Design - Manufacturing Simulating Design - Manufacturing Integration Integration Design Design Design Product Design Libraries Design Design Design Yield Modeler Yield Modeler Analyzer Analyzer Yield Modeler Analyzer Manufacturing Models Design Manufacturability Components Yield Impact Yield Impact Yield Impact Matrix Matrix Matrix Characterization Characterization Characterization Characterization Characterization Characterization Vehicles Vehicles Vehicle Analysis Vehicle Analysis Vehicles Vehicle Analysis Design and Process Process Recipe Improvements Manufacturing Manufacturing Manufacturing 21-Mar-00 • 11 • PDF Solutions, Inc.
The Yield Impact Matrix The Yield Impact Matrix Pre-tapeout SRAM Defect Layout-Process Device IP Layouts Product Layouts Layouts CV Data CV Data CV Data Layout Attributes Yield Models Yield Impact Design Yield Impact Matrix Defectivity Dependent Overall Chip 85.7% 58.0% 49.8% Product A Block A 95.0% 93.0% 88.4% Block B 95.0% 65.0% 61.8% Virgin Cache 80.0% 80.0% 64.0% Cache w/ Repair 95.0% 96.0% 91.2% 21-Mar-00 • 12 • PDF Solutions, Inc.
Using Simulated Integration Results to Make Using Simulated Integration Results to Make Production Decisions Production Decisions Design Foundry specific Predict Fab yield models Make fix Specific Yield of module failure rates Yes Design Mask Data Feedback to Yes No No Block yield Processing product redesign? issue? fix? group Production selection Internal External Shrink Tape out Tape out Redesign Tape out 21-Mar-00 • 13 • PDF Solutions, Inc.
Example 1: Via Short Flow CV Example Example 1: Via Short Flow CV Example Floorplan Floorplan • Via1/Via2/Contact Loading: Compute yield impact of density. • Via2/Contact Misalignment: Compute yield impact of misalignment Long Runners of via to underlying layers. Via1 Loading Long Runners Long Runners • Redundancy: Via2 Contact Isolated Compare fault rates of single via Loading Loading Vias chains to redundant via chains. Via2 Contact Misalignment Misalignment • Size: Redundancy Size Compute yield impact of via size. Check process margin. • Long Runners: Compute yield impact of long metal runs in via chain. 21-Mar-00 • 14 • PDF Solutions, Inc.
Example 1: Yield Modeling Example 1: Yield Modeling Process Specific Via Yield Model Process Specific Via Yield Model Single Vias Single Vias density density Redundancy = 2 density density Redundancy = 2 Via Yield Model: Y via(non-redundant) = f 1 (misalignment, density, N) Y via-redundant) = f 2 (misalignment, density, N) 21-Mar-00 • 15 • PDF Solutions, Inc.
Example 1: Design Yield Entitlement Example 1: Design Yield Entitlement Product Specific Via Yield Prediction Product Specific Via Yield Prediction Via Yield Model: Y via(non-redundant) = f 1 (misalignment, density, N) Y via-redundant) = f 2 (misalignment, density, N) Border Size (um) Yield Modeler 100% Via-density 80% Product A Product A Yield 60% 40% 20% Via-density Product B 0% 0.02 0.04 0.06 0.08 Product A Product B Misalignment Data Product B 21-Mar-00 • 16 • PDF Solutions, Inc.
Example 2: Optimizing Fill For Performance Example 2: Optimizing Fill For Performance and Yield and Yield Questions about dummy fill algorithm: G Which layers? G What pattern? G Should you exclude sections of the design layout? Approach G Build vehicle to characterize performance/yield dependencies on layout choice G Build yield models G Optimize dummy fill for product chips 21-Mar-00 • 17 • PDF Solutions, Inc.
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