Platform Based Design: Report from the Front Sagheer Ahmad Kambiz Khalilian Daniel Martin EDP-2002 Apr 22, 2002
Presentation Topics • Introduction: Embedded System design flow • Need of a higher level of abstraction of hw • HW Design Platform • TriCore based design platform – Platform details – Configurability of hardmacro of uP, Memories, & Busses • Results: SoCs based on TriCore • Conclusion 2
Embedded System (or HW/SW co-) Design Flow - A Simple view System Behavior Perf. insufficient Partitioning Co-simulation Partitioned Spec. HW development SW development Func Verif. Formal (& Func) Verification Partition into blocks &Un-optimized HW Logic Synthesis Back End(FP & PnR) Standard components Board Level Prototype Physical Prototype 3
HW components of an Embedded Sys. • Embedded Systems are implemented as mixed sw-hw systems. SW is, generally, used for features and flexibility, and HW is used for performance {e.g. Cameras, cellphones, industrial controllers, etc.}. • Compute Engine: Microcontroller, uP/uC (RISC), DSP • Program and Data Cache/Memories (Varying Size) • One or more Buss-Interconnects • Application specific HW • DMA, Interrupt support • General Purpose Peripherals 4
HW components of an Embedded Sys. • General Purpose Peripherals (GPP): – ASC: Async./Sync. Serial Interface – SSC: High Speed Synch. Serial Control – UART: Universal Asynchronous Rx/Tx – IIC: Inter-Integrated Circuit, Serial Bus – RTC: Real Time Clock – STM: System Timer – GPTU: 3x 32-bit General Purpose Timers – GPIO: Up to 64 General Purpose I/O – WDT: Watch Dog Timer – …. etc. 5
HW Design Platform System SoC Development Memory App. Specific blocks Ext. bus I/F Platform layer Bus-arbiters & Bus bridge Design Platform GPP& DMem & IMem & Configurable DMA DCache ICache Compute Engine 6
HW Design Platform (cont..) From the platform (GUI or HDL): Value-added • RISC @200Mhz worst,250MIPs Blocks • DSP @200 Mhz worst, 300MMs App Specific Cache/Mem • IMem (32KB), Icache(16KB) (IP) • DMem(32 KB), Dcache(16KB) • GPPs (ASC,RTC,I2C,STM,GPT,GIO) Interconnects • DMA, & Interrupt service Peripherals uP/DSP Develop HDL: • Application specific blocks • System Memory (compiler generated) • Top level interconnect signal hook-up. 7
Platform Deliverables • RTL with synthesis scripts (For soft-macro) • Timing shell, Timing Analysis scripts, Backend views (For Hardmacro) • Bus Function models for bus interconnects • High level compute-engine model – ISS and/or Cycle-Accurate • High level models for GPPs • Verification environment/methodology • Basic Software – Boot code, basic handler, test-programs*, Tests vectors – RTOS 8
Platform Deliverables (optional) • Emulation – FPGA-portable or Platform IP on FPGA – Platform-chip • Performance Evaluation & Analysis Support (sw/hw) – Cache hit/miss rates GUI – MMU Pages hit/miss rate Platform – Communication traffic (i.e. bus utilization) – Memory traffic Configuation Tool – Interrupt rate & response time Parameters • Configuration Tools Platfrom Derivative Verilog, VHDL etc 9 12m
Embedded System (or HW/SW co-) Design Flow with Design Platform System Behavior Perf. insufficient Partitioning Co-simulation Partitioned Spec. HW development SW development Func Verif. Func Verif. Formal (& Func) Formal (& Func) Verification Verification Un-optimized HW IP HW & Integ Logic Synthesis Back End(FP & PnR) Standard components Board Level Prototype Physical Prototype 11
TriCore - TC1 Architecture Overview • 32-bit Unified RISC+DSP TC1 CPU • Load/Store Architecture • HW controlled context saving • Fast context switch (shadow registers) Program Memory Interface • Fast interrupt response (~6 clocks) • Superscalar: Three pipelines Data Address Coprocessor Register Registers s Pipeline Control • Zero Overhead loop Branch I nt e ge r Load/Store M M U Predict Unit ALU Unit • 16-bit / 32-bit Instruction Format Data & Arithmetic MAC Instruction ALU Alignment • Single-cycle dual MAC Bit Instruction Memory Processing Fetch Protection Unit – 32x32, 16x32, Dual 16x16 • On-Chip debug support Data Memory Interface • MMU, COP • TC1 (300Mhz, typ, 0.18u), TC2 (600Mhz,typ, 0.13u) 12
TriCore1 SOC Platform - TCSOC CPS STM Interrupt Unit Program Memory Debug/ SCU Emulation FPI I/F TriCore1 CPU BCU Flexible Peripheral Interconnect Bus Program Memory Interface TCU Local Memory Bus (LMB) Data Address Coprocessor GPIO Register Registers s Pipeline Control Branch I nt e ge r Load/Store RTC Predict Unit M M U ALU Unit Data & Arithmetic MAC Instruction ALU GPTU Alignment Bit Instruction Memory Processing Fetch Protection Unit SSC x 2 ASC x 2 Data Memory Interface Bus IIC Bridge PCP Data Memory 13 EBU
TCSOC: Compute Engine,TriCore1 • TriCore1 Microprocessor System (MPS) • Configurable Program & Data Cache/Memory I/F • optional MMU and FPU. • PCP : 32-bit Peripheral Control Processor Processor • 64 (low latency) & 32 bit busses • Set of System- and General Purpose Peripherals: – ASC: Async./Sync. Serial Interface – IIC: Two channel I2C Serial Bus – RTC: Real Time Clock – SSC: High Speed Synch. Serial Control (SPI-compatible) – STM: System Timer – GPTU: 3x 32-bit General Purpose Timers – GPIO: Customizable General Purpose I/O – EBU: External Bus Interface for Off-Chip Memory – Test Control Unit (OCDS & JTAG I/F) – System Control Unit (Reset Control, Power Management,Watch Dog Timer) 14
TCSOC: Design & Arch considerations Interrupt PMI • Partitioning based on CPU Memory functionality Bus I/F DMI MMU DTAG PTAG • Partitioning based on reusability Data Program Program Mem MPU Mem Mem SIU (FPI bus I/F + LMB I/F + Debug/Int) 15
Design & Arch considerations (II) Code/Data Memories • Configurable selection between mem & cache • All pins abutt w/o routing MPU • eight block on either side 17
TCSOC: Bus Interconnects (LMB & FPI) • TC1 MPS : TriCore1 Microprocessor System • Configurable Program & Data Cache/Memory I/F • optional MMU and FPU. • PCP : 32-bit Peripheral Control Processor • 64 (low latency) LBM, & 32 bit FPI • Set of System- and General Purpose Peripherals: – ASC: Async./Sync. Serial Interface – IIC: Two channel I2C Serial Bus – RTC: Real Time Clock – SSC: High Speed Synch. Serial Control (SPI-compatible) – STM: System Timer – GPTU: 3x 32-bit General Purpose Timers – GPIO: Customizable General Purpose I/O – EBU: External Bus Interface for Off-Chip Memory – Test Control Unit (OCDS & JTAG I/F) – System Control Unit (Reset Control, Power Management,Watch Dog Timer) 22
TCSOC: Bus Interconnects (cont..) MPU • 64 bit on-chip & off-chip Mem Mem bus I/F • 32 bit on-chip & off-chip bus I/F • Large no. of peripherals? SIU • System bus & cpu freq Local bus Bus bridge 64 bit ratio 1:1, 1:2, …, 1:n 64 bit – Signal configurable 32 bit system bus ……... per0 perN per1 24
TCSOC: Interrupt System • Independent Interrupt MPU Dmem Pmem Control Unit • 255 interrupts, connected with 7bit arbitration bus • ICU freq ratio 1:1, 1:2, …, 1:n SIU ICU – Signal configurable • Interrupt bus cycle 1 or 2 of CPU clock cycle Interrupt bus (7 bit) OR-tree – Register configurable ……... per0 perN per1 26
Telematics Controller – TC1920 29
Triple-Mode Baseband IC MPU 30
Conclusion Design Platform: • High-performance configurable RISC/DSP • Bus interconnects (at least one low latency) • General Purpose Peripherals • PCP, and Interrupt system By Using Design Platform: • Quick development of derivative designs (i.e. SoC). • Designer concentrates on system design rather than components • Designer uses a proven design methodology 31
EDP-2002 Never Stop Thinking Sagheer Ahmad Kambiz Khalilian Daniel Martin http://www.infineon.com/tricore/
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