[PPT] - Path-Based Edge Activation for Dynamic Run-Time Scheduling Vincent PowerPoint Presentation

SLIDE 1

Path-Based Edge Activation for Dynamic Run-Time Scheduling

Vincent J. Mooney III Vincent J. Mooney III

Assistant Professor Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA USA

SLIDE 2

Outline

Motivation

Motivation

Previous Work

Previous Work

Path

Path-

Based Edge Activation

Based Edge Activation

Example

Example

Synthesis Flow

Synthesis Flow

Experimental Results

Experimental Results

Future Work

Future Work

SLIDE 3

Motivation

Dynamic Hard

Dynamic Hard-

Real

Real-

Time Systems

Time Systems

Previous work by author limited to

Previous work by author limited to DAGs DAGs

Application examples have control flow

Application examples have control flow

Extend run

Extend run-

time system to handle CDFG

time system to handle CDFG

SLIDE 4

Robotics Example: Concurrent Control Laws

singular Ohold Law

h3
h2

saturate velocity find jacobian matrix vector multiply 1 1

SLIDE 5

Previous Work

“Scheduling of Conditional Process Graphs

“Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems,” for the Synthesis of Embedded Systems,” Eles Eles, et. al., DATE, 1998. , et. al., DATE, 1998.

“Hardware/Software Co

“Hardware/Software Co-

Design of Run

Design of Run-

Time Systems,”

Time Systems,” Ph Ph.D. thesis, Stanford, .D. thesis, Stanford, 1998. 1998.

“Hardware/Software Co

“Hardware/Software Co-

Design of Run

Design of Run-

Time Schedulers for Real

Time Schedulers for Real-

Time Systems,”

Time Systems,” to appear in Design Automation of to appear in Design Automation of Embedded Systems. Embedded Systems.

SLIDE 6

Conditional Process Graphs: Figure 4 (page 136), Processor pe2

P17 P14 P11 P3 a) Optimal schedule of the path corresponding to D^C^K P17 P15 b) Optimal schedule of the path corresponding to D^C^K’ P17 P14 P3 c) Adjusted schedule of the path corresponding to D^C^K P11 P3 P11

SLIDE 7

Conditional Process Graphs

Conditionals (e.g., D, C, K) are broadcast to

Conditionals (e.g., D, C, K) are broadcast to all processing elements all processing elements

Activation times (start times) for tasks fixed

Activation times (start times) for tasks fixed based on values of conditionals (or subset of based on values of conditionals (or subset of conditionals) conditionals)

Focus on handling late arriving conditionals

Focus on handling late arriving conditionals

In case where all conditionals are ready at

In case where all conditionals are ready at the beginning, the beginning, schedule merging schedule merging may result may result in known in known suboptimal suboptimal solution solution

SLIDE 8

Previous Work (author)

RTS.v done start V1 done start RAM CPU core1 memory controller CPU Interface int 64 start done Vn done start

SLIDE 9

Task Control

Associate

Associate start start and and done done event with each task event with each task

Control of hardware tasks

Control of hardware tasks

start

start signal (bit) signal (bit)

done

done signal (bit) signal (bit)

Control of software tasks

Control of software tasks

start

start vector encapsulates all vector encapsulates all sw sw start start events events

done

done vector encapsulates all vector encapsulates all sw sw done done events events

SLIDE 10

Run Time Scheduler Implementation

Start with control flow of

Start with control flow of hw hw-

and

and sw sw-

tasks

tasks

Hardware implementation:

Hardware implementation:

put FSM corresponding to the control flow

put FSM corresponding to the control flow

cycle based semantics

cycle based semantics

can predictably satisfy hard real

can predictably satisfy hard real-

time constraints

time constraints

Software implementation:

Software implementation:

preemptive static priority scheduler

preemptive static priority scheduler

can execute different threads

can execute different threads

keeps track of which threads are suspended

keeps track of which threads are suspended

direct execution of software tasks by ISR

direct execution of software tasks by ISR

all

all sw sw tasks run to completion (no suspension) tasks run to completion (no suspension)

Mixed implementation can leverage advantage of

Mixed implementation can leverage advantage of hardware and software hardware and software

SLIDE 11

src

h0

mvm2 cjd cg snk

h1

fk mvm3 mvm4 mvm1

x3k f3(t3,x3k) t3

h1,snk cjd,snk f3*(t3,x3k) x3k*
h0 24,020

24,020 oh1,snk

h1

43,812 43,812 cjd,snk cjd 35,012 35,012 oh1,snk

∞ ∞ ∞

X2* = {(oh0,oh1,snk),(oh1,cjd,snk), (cjd,oh1,snk)}

Constructive Heuristic

n DAG

NEVER = {oh0,oh1,cjd}

SLIDE 12

src

h0

mvm2 cjd cg snk

h1

fk mvm3 mvm4 mvm1 Final Result:

h0 -- priority 1

cjd -- priority 2

h1 -- priority 3

WCET: 39,012

Constructive Heuristic Scheduling Algorithm: Result

SLIDE 13

Path-Based Edge Activation

Extend scheduling to handle CDFG, not just DAG

Extend scheduling to handle CDFG, not just DAG

Conditional edges

Conditional edges

active only if a particular path chosen

active only if a particular path chosen

a path is defined by a set of values of conditional

a path is defined by a set of values of conditional choices in the CDFG choices in the CDFG

For each path, insert conditional edges to minimize

For each path, insert conditional edges to minimize WCET WCET

assumption: conditional values evaluated early

assumption: conditional values evaluated early enough for all conditional edge insertions enough for all conditional edge insertions

SLIDE 14

src

h0

cg cjd mvm snk

h1

fk task hw/sw wcet(cycles)

---- ---------- ---------------

cg hw 11,000

h0

sw 2,554

h1

sw 20,581 fk hw 11,500 cjd sw 14,878 mvm hw 4,400 NEVER = {oh0, oh1, cjd}

c=1 c=1 c=0 c=0

No static order can achieve better than a WCET of 49,013

Example

SLIDE 15

Centralized Control

Done signals arrive to hardware run

Done signals arrive to hardware run-

time

time scheduler (no broadcast) scheduler (no broadcast)

Dynamic ordering of software tasks must be

Dynamic ordering of software tasks must be done by hardware run done by hardware run-

time scheduler

time scheduler

Use

Use hardware hardware-

driven software execution

driven software execution

ISR executes a software task

ISR executes a software task

adv

adv.: fast .: fast

disadv

disadv.: software tasks not .: software tasks not interruptable interruptable

SLIDE 16

Scheduling Assumptions

A CDFG represents the set of tasks

A CDFG represents the set of tasks

limited number of paths

limited number of paths

One rate constraint for the graph

One rate constraint for the graph

A NEVER set specifies mutually exclusive

A NEVER set specifies mutually exclusive sw sw-

tasks

tasks

Each

Each sw sw-

task, once started, runs to completion

task, once started, runs to completion

limits solution space

limits solution space

Hw

Hw-

sw

sw communication accounted for communication accounted for

in task WCET

in task WCET

as a separate task

as a separate task

Interrupts come only from the

Interrupts come only from the hw hw run run-

time

time sched sched. .

SLIDE 17

src

h0

cg cjd mvm snk

h1

fk

c=1 c=1 c=0 c=0 c=0 c=1 c=1

CDFG

SLIDE 18

src

h0

cg cjd mvm snk

h1

fk

c=1 c=1 c=0 c=0 c=0 c=1 c=1

src

h0

cjd mvm snk

h1

fk

c=1 c=1 c=1 c=1

case: c=1 CDFG WCET = 38,013

SLIDE 19

src

h0

cg cjd mvm snk

h1

fk

c=1 c=1 c=0 c=0 c=0 c=1 c=1

src

h0

cg cjd mvm snk

h1

c=0 c=0 c=0

CDFG case: c=0 WCET = 39,859

SLIDE 20

src

h0

cg cjd mvm snk

h1

fk

c=1 c=1 c=0 c=0 c=0 c=1 c=1

WCET of 39,859 achievable with dynamic order case: c=1 CDFG case: c=0 src

h0

cjd mvm snk

h1

fk

c=1 c=1 c=1 c=1

src

h0

cg cjd mvm snk

h1

c=0 c=0 c=0

SLIDE 21

Algorithm

Solve_order(CDFG,NEVER)

beginmodule foreach path determined by a unique set of conditional values begin DAG = subset of CDFG determined by path Schedule DAG using constructive heuristic scheduling Add conditional edges to enforce DAG schedule end endmodule

SLIDE 22

Tool Flow

behavioral Verilog C constraints

Fifos, RAM, etc. Mp core, RAM size, etc.

RTS.c *.c

RAM

RTS.v

V1

behavioral Verilog RTL Verilog

BC DC BC System Specification Interface Generation Serra2 Run-Time Scheduler Synthesis Interface Vn w c e t Cinderella-M wcet

SLIDE 23

SERRA2 Run-Time Scheduler Synthesis Tool

constraints behavioral Verilog C relocatable assembly RTS assembly code cfe cdfg RTS control FSM in RTL Verilog sw-tasks assembly code

Thalia2 Diego GCC linker

dataflow analysis

Key:

= data = tool = tool

Clara2

ISR template

Cind-M wcet BC wcet

System Specification

conditional edges

SLIDE 24

Example and Experimental Results

Hw

Hw-

tasks

tasks written in written in Verilog Verilog for for BC, use LSI BC, use LSI 10K library 10K library

Verilog

Verilog model model

f MIPS core
f MIPS core

with interrupts with interrupts

19% decrease

19% decrease in WCET: in WCET: 39859 (49013) 39859 (49013)

Used VCS

Used VCSTM

TM

to verify result to verify result

Software Task # Lines

f C

# Lines Asmbly WCET cjd 286 1177 14878

h0

90 237 2554

h1

693 3263 20581 int-ser-rtn N/A 26 20

Hw-task # Lines V Area WCET mvm 629 33645 4400 fk 2362 42168 11500 cg 2897 59587 11000 rtsched-hw 484 413 99701

SLIDE 25

Future Work

Extend to handle late arriving conditionals

Extend to handle late arriving conditionals

Extend to allow