Path-Based Edge Activation for Dynamic Run-Time Scheduling Vincent J. Mooney III Vincent J. Mooney III Assistant Professor Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA USA
Outline � Motivation Motivation � � Previous Work Previous Work � � Path Path- -Based Edge Activation Based Edge Activation � � Example Example � � Synthesis Flow Synthesis Flow � � Experimental Results Experimental Results � � Future Work Future Work �
Motivation � Dynamic Hard Dynamic Hard- -Real Real- -Time Systems Time Systems � � Previous work by author limited to Previous work by author limited to DAGs DAGs � � Application examples have control flow Application examples have control flow � � Extend run Extend run- -time system to handle CDFG time system to handle CDFG �
Robotics Example: Concurrent Control Laws singular 0 1 Ohold find jacobian Law matrix vector multiply oh2 1 0 saturate velocity oh3
Previous Work � “Scheduling of Conditional Process Graphs “Scheduling of Conditional Process Graphs � for the Synthesis of Embedded Systems,” for the Synthesis of Embedded Systems,” Eles, et. al., DATE, 1998. , et. al., DATE, 1998. Eles � “Hardware/Software Co “Hardware/Software Co- -Design of Run Design of Run- - � Time Systems,” Ph Ph.D. thesis, Stanford, .D. thesis, Stanford, Time Systems,” 1998. 1998. � “Hardware/Software Co “Hardware/Software Co- -Design of Run Design of Run- - � Time Schedulers for Real- -Time Systems,” Time Systems,” Time Schedulers for Real to appear in Design Automation of to appear in Design Automation of Embedded Systems. Embedded Systems.
Conditional Process Graphs: Figure 4 (page 136), Processor pe 2 P3 P11 P14 P17 a) Optimal schedule of the path corresponding to D^C^K P11 P3 P15 P17 b) Optimal schedule of the path corresponding to D^C^ K’ P11 P3 P14 P17 c) Adjusted schedule of the path corresponding to D^C^K
Conditional Process Graphs � Conditionals (e.g., D, C, K) are broadcast to Conditionals (e.g., D, C, K) are broadcast to � all processing elements all processing elements � Activation times (start times) for tasks fixed Activation times (start times) for tasks fixed � based on values of conditionals (or subset of based on values of conditionals (or subset of conditionals) conditionals) � Focus on handling late arriving conditionals Focus on handling late arriving conditionals � � In case where all conditionals are ready at In case where all conditionals are ready at � the beginning, schedule merging the beginning, schedule merging may result may result in known suboptimal suboptimal solution solution in known
Previous Work (author) CPU core1 start done 64 CPU Interface int RAM memory controller RTS.v start start start done done done V1 Vn
Task Control � Associate � Associate start start and and done done event with each task event with each task � Control of hardware tasks � Control of hardware tasks start signal (bit) signal (bit) � start � done signal (bit) signal (bit) � done � � Control of software tasks � Control of software tasks start vector encapsulates all vector encapsulates all sw sw start start events events � start � done vector encapsulates all vector encapsulates all sw sw done done events events � done �
Run Time Scheduler Implementation � Start with control flow of � Start with control flow of hw hw- - and and sw sw- -tasks tasks � Hardware implementation: � Hardware implementation: � put FSM corresponding to the control flow put FSM corresponding to the control flow � � cycle based semantics cycle based semantics � � can predictably satisfy hard real can predictably satisfy hard real- -time constraints time constraints � � Software implementation: � Software implementation: � preemptive static priority scheduler preemptive static priority scheduler � � can execute different threads can execute different threads � � keeps track of which threads are suspended keeps track of which threads are suspended � � direct execution of software tasks by ISR direct execution of software tasks by ISR � all sw sw tasks run to completion (no suspension) tasks run to completion (no suspension) � all � � Mixed implementation can leverage advantage of � Mixed implementation can leverage advantage of hardware and software hardware and software
NEVER = src {oh0,oh1,cjd} Constructive Heuristic on DAG cg oh0 cjd x 3k f 3 (t 3 ,x 3k ) fk oh1 t 3 oh1,snk cjd,snk f 3 *(t 3 ,x 3k ) x 3k * mvm2 ∞ oh0 24,020 24,020 oh1,snk ∞ oh1 43,812 43,812 cjd,snk mvm3 mvm1 ∞ cjd 35,012 35,012 oh1,snk mvm4 X 2 * = {(oh0,oh1,snk),(oh1,cjd,snk), (cjd,oh1,snk)} snk
Constructive Heuristic src Scheduling Algorithm: cg Result oh0 cjd fk oh1 Final Result: mvm2 -------------------- oh0 -- priority 1 cjd -- priority 2 mvm3 mvm1 oh1 -- priority 3 WCET: 39,012 mvm4 snk
Path-Based Edge Activation � Extend scheduling to handle CDFG, not just DAG Extend scheduling to handle CDFG, not just DAG � � Conditional edges Conditional edges � active only if a particular path chosen � active only if a particular path chosen � a path is defined by a set of values of conditional � a path is defined by a set of values of conditional � choices in the CDFG choices in the CDFG � For each path, insert conditional edges to minimize For each path, insert conditional edges to minimize � WCET WCET � assumption: conditional values evaluated early assumption: conditional values evaluated early � enough for all conditional edge insertions enough for all conditional edge insertions
Example src task hw/sw wcet(cycles) mvm ----- ---------- --------------- oh0 cg hw 11,000 oh0 sw 2,554 cjd oh1 sw 20,581 oh1 c=1 fk hw 11,500 c=0 c=1 c=0 cjd sw 14,878 cg mvm hw 4,400 fk snk NEVER = {oh0, oh1, cjd} No static order can achieve better than a WCET of 49,013
Centralized Control � Done signals arrive to hardware run Done signals arrive to hardware run- -time time � scheduler (no broadcast) scheduler (no broadcast) � Dynamic ordering of software tasks must be Dynamic ordering of software tasks must be � done by hardware run- -time scheduler time scheduler done by hardware run � Use Use hardware hardware- -driven software execution driven software execution � � ISR executes a software task ISR executes a software task � adv.: fast .: fast � adv � � disadv disadv.: software tasks not .: software tasks not interruptable interruptable �
Scheduling Assumptions � A CDFG represents the set of tasks � A CDFG represents the set of tasks � limited number of paths limited number of paths � � One rate constraint for the graph � One rate constraint for the graph � A NEVER set specifies mutually exclusive � A NEVER set specifies mutually exclusive sw sw- -tasks tasks � Each � Each sw sw- -task, once started, runs to completion task, once started, runs to completion limits solution space � limits solution space � � Hw � Hw- -sw sw communication accounted for communication accounted for in task WCET � in task WCET � as a separate task � as a separate task � � Interrupts come only from the � Interrupts come only from the hw hw run run- -time time sched sched. .
CDFG src mvm oh0 c=1 c=1 cjd c=0 oh1 c=1 c=0 c=1 c=0 cg fk snk
case: c=1 CDFG src src mvm mvm oh0 oh0 c=1 c=1 c=1 c=1 cjd cjd c=0 oh1 oh1 c=1 c=1 c=0 c=1 c=1 c=0 cg fk fk snk snk WCET = 38,013
CDFG case: c=0 src src mvm mvm oh0 oh0 c=1 c=1 cjd cjd c=0 c=0 oh1 oh1 c=1 c=0 c=0 c=1 c=0 c=0 cg cg fk snk snk WCET = 39,859
case: c=1 CDFG case: c=0 src src src mvm mvm mvm oh0 oh0 oh0 c=1 c=1 c=1 c=1 cjd cjd cjd c=0 c=0 oh1 oh1 oh1 c=1 c=0 c=1 c=0 c=1 c=0 c=1 c=0 cg cg fk fk snk snk snk WCET of 39,859 achievable with dynamic order
Algorithm Solve_order(CDFG,NEVER) beginmodule foreach path determined by a unique set of conditional values begin DAG = subset of CDFG determined by path Schedule DAG using constructive heuristic scheduling Add conditional edges to enforce DAG schedule end endmodule
Tool Flow System Specification behavioral Verilog constraints C Cinderella-M wcet Fifos, Serra2 Run-Time Mp core, Interface Generation RAM, Scheduler Synthesis RAM size, etc. etc. t behavioral Verilog e RTL Verilog c w BC DC BC RTS.c *.c V1 Vn RAM RTS.v Interface
SERRA2 Run-Time Scheduler Synthesis Tool System Specification C constraints behavioral Verilog dataflow analysis Cind-M GCC Diego BC wcet cdfg relocatable assembly wcet cfe ISR template Clara2 conditional linker Thalia2 edges Key: sw-tasks = data assembly code RTS control FSM = tool in RTL Verilog RTS assembly code = tool
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