Outcomes I can create a state diagram to solve a sequential problem - PowerPoint PPT Presentation

15.1 15.2 Outcomes • I can create a state diagram to solve a sequential problem • I can implement a working state machine given a state diagram Unit 15 State Machine Design 15.3 15.4 State Machines • (Finite) state machines of (FSMs) provide the “brains” or control for electronic and electro-mechanical systems • We've implemented state machines in software, now let's see how we can build them in hardware • We use the state to help us know which step of an algorithm we are currently at • Goal is to generate output values at __________________ – When you need time dependent outputs, you can use an FSM STATE MACHINES OVERVIEW • FSMs require __________ and _____________ logic elements – Sequential Logic to remember what step (state) we’re in • Encodes everything that has happened in the past – Combinational Logic to produce outputs and find what state to go to next • Generates outputs based on what state we’re in and the input values

15.5 15.6 State Machine Example Another State Diagram Example • Design a sequence detector to check for the combination • “101” Sequence Detector should output F=1 when the "101" sequence 101 is found in consecutive order • Input, X, provides 1-bit per clock • Check the sequence of X for "101" in successive clocks • If "101" detected, output Z=1 (Z=0 all other times) S101 Sinit S1 S10 F=0 F=0 F=0 F=1 "101" X Sequence Z Detector CLK RESET State Diagram for “101” Sequence Detector See the end of this slide set for more detailed solutions and explanations. 15.7 15.8 Correct Specification of State Diagrams Correct Specification of State Diagrams 2 • Exactly one transition from a state may be true at a • For HW especially, it is critical that exactly __________ time from a state may be true at a time – Make sure the conditions you associate with the arrows – We can't go __________ at once and if we don't tell it explicitly coming out of a state are _________________ (< 2 true) where to go next, it may go to any random state but all inclusive (> 0 true) – If you want to stay in a state, include an explicit ________ arrow • On the 2 nd example if you want to stay in Q1, include a loopback labeled X=0 ALWAYS double check your transitions to ensure they are mutually exclusive.

15.9 15.10 State Machines State Machine NEXT STATE • The HW for a state machines can be broken CURRENT STATE The FF inputs will be the The FF outputs into 3 sections of logic value of the next state (on represent the current the next clock edge the FF state (the state we’re outputs will change based in right now) – State Memory (SM) on the inputs) • Just FF’s to remember the ________________ inputs – ____________ Logic (NSL) next current Next State Logic State Output outputs state state Memory Function • Combo logic to determine the next state Q i D i (Flip- Logic • Essentially implements the transition conditions Flops) – ____________ Logic (OFL) • Combo logic to produce the outputs clock Important : State is always represented and stored by the flip-flop outputs in the system 15.11 15.12 State Machines • Below is a circuit implementing a state machine, notice how it breaks into the 3 sections (Input) (Next State) (Current State) X D 0 Q 0 OFL D Q (Output) NSL Q F SM D 1 Q 1 D Q STATE MACHINE DESIGN Q CLK

15.13 15.14 State Diagram vs. State Machine State Machine Design State Diagrams State Machine • State machine design involves taking a 1. States 1. State Memory => FF’s problem description and coming up with a – n-FF’s => 2 n states 2. Transition Conditions 2. Next State Logic (NSL) state diagram and then designing a circuit to 3. Outputs – combinational logic implement that operation – logic for FF inputs 3. Output Function Logic (OFL) State Machines require sequential logic to – MOORE: f(state) remember the current state – MEALY: f(state + inputs) (w/ just combo logic we could only look at the current value of X, but now we can take 4 separate Problem Circuit (Input) (Next State) (Current State) State Diagram actions when X=0) X D 0 Q 0 Description Implementation OFL D Q X=1 (Output) On Reset (power on) NSL X=1 X=0 X=1 Q F S101 Sinit S1 S10 SM F=0 F=0 F=0 F=1 X=0 D 1 Q 1 X=1 D Q X=0 X=0 Q State Diagram for “101” Sequence Detector CLK 15.15 15.16 State Machine Design • Coming up with a state diagram is non-trivial Requires creative solutions • • Designing the circuit from the state diagram is done according to a simple set of steps • To come up w/ a state diagram to solve a problem – Write out an algorithm or ____________ to solve the problem EXAMPLE 1 – Each step in your algorithm will usually be _________ in your state diagram Ask yourself what past inputs need to be ____________ – and that will usually lead to a state representation

15.17 15.18 Alternating Detector Alternating Detector • Design a state machine to check if sensor produces two 0’s in • Given bits coming in from a sensor, design a a row (i.e. 2 consecutive spaces) or two 1’s in a row (i.e. 2 system that outputs true if the previous 2 input consecutive teeth) bits alternate (are the same) or false if the same •G10 = Last cycle we got 1, bit value is detected in that past two clock S = two cycles ago we got 0 cycles G01 G10 •G01 = Last cycle we got 0, A=1 A=1 two cycles ago we got 1 – What do you need to remember? The ______ bits. Output •G11 = Got 2 consecutive 1’s S = •G00 = Got 2 consecutive 0's A S G00 G11 Alternating A=0 A=0 Detector Current State CLK RST 15.19 15.20 Transition Output Table 6 Steps of State Machine Design 1. State Diagram • Convert state diagram to transition/output table – Show Next State & Output as a function of Current State and Input 2. Transition/Output Table Current Input (S) Next Output 3. State Assignment On Reset S = 0 (power on) State State (A) S = 1 Determine the # of FF’s required • G01 G10 G01 0 1 A=1 A=1 S = 0 • Assign binary codes to replace symbolic names G01 1 1 S = 0 4. Excitation Table (Rename Q* to D) S = 1 S = 1 G11 0 0 5. K-Maps for NSL and OFL G00 G11 G11 1 0 A=0 A=0 G00 0 0 • One K-Map for every FF input S = 0 S = 1 G00 1 0 • One K-Map for every output of OFL G10 0 1 6. Draw out the circuit G10 1 1

15.21 15.22 Transition Output Table Transition Output Table • Now assign binary codes to represent states • Convert state diagram to transition/output table Next State On Reset Current State Output S = 0 Current Input Next State Output (power on) S = 0 S = 1 S = 1 State G01 G10 A=1 A=1 S = 0 State Q 1 Q 0 State State A Q1 Q0 S Q1* Q0* A S = 0 S = 1 S = 1 G01 0 0 G00 1 0 G10 1 1 1 0 0 0 1 0 1 G00 G11 G11 0 1 G01 0 0 G11 0 1 0 0 0 1 1 1 1 A=0 A=0 S = 0 S = 1 0 1 0 0 0 0 G10 1 1 G01 0 0 G11 0 1 1 0 1 1 0 1 0 State Assignment Mapping G00 1 0 G00 1 0 G10 1 1 0 State Q 1 Q 0 1 0 0 1 0 0 On Reset S = 0 (power on) Here we have redrawn the 8 G01 0 0 S = 1 1 0 1 1 1 0 G01 G10 row table from the previous A=1 A=1 S = 0 G11 0 1 slide into 4 rows & 2 columns. 1 1 0 0 0 1 We've also separated the S = 0 S = 1 S = 1 G00 1 0 1 1 1 0 1 1 output A since it doesn't G00 G11 depend on S but only Q1 and G10 1 1 A=0 A=0 Q0 S = 0 S = 1 15.23 15.24 Excitation Table Excitation Table • Using your transition table you know what you want Q* • The goal is to produce logic for the inputs to the FF’s to be, but how can you make that happen? (D 1 ,D 0 )…these are the excitation equations • For D-FF’s Q* will be whatever ___________________ OFL OFL (Output (Output NSL SM NSL SM (Next State Logic) (State Memory) Function Logic) (Next State Logic) (State Memory) Function Logic) S D 0 S D 0 Q 0 (t) Q 0 (t) D Q D Q CLK CLK A A D 1 D 1 Q 1 (t) Q 1 (t) D Q D Q CLK CLK CLK CLK Q 1 (t) Q 1 (t) Current State Feedback Current State Feedback Q 0 (t) Q 0 (t)

15.25 15.26 Excitation Table Karnaugh Maps • In a D-FF Q* will be whatever D is, so if we know what we want • Now need to perform K-Maps for D1, D0, and A Q* to be just make sure that’s what the D input is Next State Current State Output S = 0 S = 1 Next State State Q 1 Q 0 State D 1 D 0 State D 1 D 0 A Current State Output S = 0 S = 1 G01 0 0 G00 1 0 G10 1 1 1 G11 0 1 G01 0 0 G11 0 1 0 State Q 1 Q 0 State D 1 D 0 State D 1 D 0 A G10 1 1 G01 0 0 G11 0 1 1 G01 0 0 G00 1 0 G10 1 1 1 G00 1 0 G00 1 0 G10 1 1 0 G11 0 1 G01 0 0 G11 0 1 0 S 0 1 Q1Q0 G10 1 1 G01 0 0 G11 0 1 1 00 G00 1 0 G00 1 0 G10 1 1 0 01 D1 = 11 10 15.27 15.28 Karnaugh Maps Karnaugh Maps • Now need to perform K-Maps for D1, D0, and A • Now need to perform K-Maps for D1, D0, and A Next State Next State Current State Output Current State Output S = 0 S = 1 S = 0 S = 1 State Q 1 Q 0 State D 1 D 0 State D 1 D 0 A State Q 1 Q 0 State D 1 D 0 State D 1 D 0 A G01 0 0 G00 1 0 G10 1 1 1 G01 0 0 G00 1 0 G10 1 1 1 G11 0 1 G01 0 0 G11 0 1 0 G11 0 1 G01 0 0 G11 0 1 0 G10 1 1 G01 0 0 G11 0 1 1 G10 1 1 G01 0 0 G11 0 1 1 G00 1 0 G00 1 0 G10 1 1 0 G00 1 0 G00 1 0 G10 1 1 0 S Q1 0 1 0 1 Q1Q0 Q0 1 0 00 0 01 1 0 1 D0 = 11 A = Q 1 ’Q 0 ’ + Q1Q0 = Q 1 XNOR Q 0 10