Optimal Partitioned Fault-Tolerant Bus Layout for Reducing Power in Nanometer Designs Shanq-Jang Ruan 1 , Edwin Naroska 2 Chun-Chin Chen 1 1 National Taiwan University of Science and Technology Taipei, Taiwan 2 Fraunhofer IMS Duisburg, Germany 1/27 NTUST ET LPS LAB
Outline • Introduction – Why do we need low power – Source of Power Dissipation – Coupling effect in deep-submicro technology – Motivation and Observation • Permutation and Spacing for Low Power Bus Design – Coupling Capacitance Model – Permutation Technique – Spacing Technique • Bus Partition Flow • Low Power Fault-Tolerant Bus Architecture • Graph Theory Algorithm for Fault-Tolerant Bus Layout Optimization • Experimental Results • Conclusion 2/27 NTUST ET LPS LAB
Introduction - Why do we need low power- • Why we need low power fault-tolerant bus design in VDSM – Power has become a critical concern for nowadays design for hand-held and high-performance systems. – In VDSM era, on-chip interconnect contribution about 15% to 30% total power dissipation in modern microprocessors. – For low power and reliability concerns, a fault-tolerant bus could be used to reducing power while increasing reliability. Battery Life Reliability 3/27 NTUST ET LPS LAB
Introduction -Source of Power Dissipation- = + + P P P P avg dynamic short leakage 1 = × × 2 ( ) P C V E sw dynamic L dd 2 4/27 NTUST ET LPS LAB
Introduction -Coupling Effect in DSM Technology- • Geometry downscaling of digital circuits (deep submicron) increases coupling capacitance C between adjacent wires A A = ε C d d This effect also introduce power dissipation Coupling power becomes significant in deep-submicro. For example, in standard 0.13µm technologies with minimum distance between bus lines, the ratio of coupling and line capacitances is great than eight. 5/27 NTUST ET LPS LAB
Introduction -Motivation and Observation- • From 12 SPEC2000 benchmark programs, the number of different transition patterns is far less than theoretical number (2 32 × 2 32 ). Prog. gzip vpr gcc mcf parser perlbmk vorex bzip2 mesa art equake ammp Tran. 5914 15546 85728 6011 12497 33408 30714 5778 13547 5302 7655 9788 Types • Signal statistics can be used to decrease coupling! 6/27 NTUST ET LPS LAB
Modeling Coupling Effect for Adjacent Wires • One wire is static � Dissipated power: λ C C • Both wires transition to same value � Dissipated power: 0 C C • Wires transition in opposite directions C C � Dissipated power: 4 λ 7/27 NTUST ET LPS LAB
Coupling Effect Table • Normalized coupling effect table new value C 00 01 10 11 00 0 1 1 0 Old 01 1 0 4 1 value 10 1 4 0 1 11 0 1 1 0 8/27 NTUST ET LPS LAB
Problem Formulation • Based on probabilities = + + ( , ) ( , ) ( , ) xtalk i j p i j p i j 00 , 01 10 , 11 p 01,00 ( i , j ), p 10,00 ( i , j ), p 11,00 + + ( , ) ( , ) p i j p i j 01 , 00 11 , 10 ( i , j ), p 00,01 ( i , j ), p 10,01 ( i , j ), + + ( , ) ( , ) p i j p i j 00 , 10 01 , 11 …, p 01,11 ( i , j ) the crosstalk + + ( , ) ( , ) p i j p i j 10 , 00 11 , 01 + caused by a wire pair ( i , j ) 4 ( , ) 4 ( , ) p i j p i j 01 , 10 10 , 01 can be formulated as: = ∑ n xtalk c eff i = 0 i • Coupling Effect between with wires: A = ε ⋅ ( , ) c xtalk w w + 1 i i i d min 9/27 NTUST ET LPS LAB
Permutation � Coupling effect (power dissipation) is dependent on signal statistics of neighboring wires w 1 w 2 w 3 W 4 W 5 w 0 10/27 NTUST ET LPS LAB
Spacing approach #1/2 • Spacing approaches – Equal spacing – Coupling aware spacing • “Equal” spacing 11/27 NTUST ET LPS LAB
Spacing approach #2/2 • Coupling between adjacent wires is typically different due to traffic • “Coupling aware” spacing 12/27 NTUST ET LPS LAB
Do We Need Extra Area for Enlarging Wire Spacing? • Example: – All digital phase locking loop (ADPLL) – Area utilization is set to 82% for routing with Astro (Synopsys) by different width:length ratios. 1 1 2 1 1 … 3 9 … … 13/27 NTUST ET LPS LAB
Bus Partition Flow • Bus Partition • Optimization with Permutation and Spacing 14/27 NTUST ET LPS LAB
Partitioned fault-tolerant bus Architecture Receiver Wire Permutation Wire Permutation Sender data bits Decoder BUS BUS & Correcter Wire Permutation Wire Permutation parity bits Parity Encoder Reduced coupling Perm Encoder Perm Decoder By spacing 15/27 NTUST ET LPS LAB
Graph Theory Algorithm for Fault- tolerant Bus Layout Optimization • Graph theory for permutation – This problem is similar to the traveling-salesman problem or finding minimum Hamilton path problem . – To find a optimization solution in a polynomial-time • Graph theory for spacing – Depend on the result of permutation – Got more coupling in neighbor wires, got more extra space in neighbor wires of bus. 16/27 NTUST ET LPS LAB
Graph theory for permutation • Using a heuristic algorithm similar to Kruskal’s minimum spanning tree algorithm. – the edge with the smallest weight is selected that does not cause a cycle and does not increase the degree of a node to more than two V1 3 3 3 V6 Transfer to graph V2 7 ⎡ 0 3 3 2 7 3 ⎤ 3 and 5 ⎢ ⎥ find the minimum 3 0 3 4 5 5 ⎢ ⎥ 5 2 hamiltonian path 2 ⎢ ⎥ 4 3 3 0 1 4 4 4 = 4 ⎢ ⎥ M 3 3 2 4 1 0 5 5 ⎢ ⎥ ⎢ ⎥ 7 5 4 5 0 4 4 V3 V5 ⎢ ⎥ 4 ⎢ ⎥ 3 5 4 5 4 0 ⎣ ⎦ 5 1 1 5 V4 17/27 NTUST ET LPS LAB
Graph theory for spacing • Using the result of permutation and extra space K to assign space V1 V2 3 V6 3 2 4 V3 1 V5 V4 × K w = i d + + ⋅ ⋅ ⋅ + i w w w − 1 2 1 n V 1 V 2 V 3 V 4 V 5 V 6 18/27 NTUST ET LPS LAB
Graph theory for spacing • Using the result of permutation and extra space K to assign space V1 V2 3 V6 3 2 4 V3 1 V5 V4 × K w = i d + + ⋅ ⋅ ⋅ + i w w w − 1 2 1 n d + d + d + d + d + d d d d d 5 min 1 min 2 min 3 min 4 min V 5 V 6 V 1 V 4 V 3 V 2 19/27 NTUST ET LPS LAB
Simulation Environment • Instruction bus of PISA processor architecture (derived from MIPS-IV ISA) • 12 SPEC2000 benchmark programs • 20% additional space • The bus is with 1000 µ m long, 0.14 µ m width and 0.25 µ m height based on 90nm technology process 20/27 NTUST ET LPS LAB
Power Reduction Compared with the Original bus Architecture perm(no extra space) perm with extra 20*dmin space perm+spacing with extra 20*dmin space 50 45 40 35 30 25 20 15 10 5 0 equake gzip vpr mesa art mcf parser perlbmk bzip2 vortex gcc ammp Fig. 9 21/27 NTUST ET LPS LAB
Power Reduction for Different Parity Bit Positions and Spacing Approaches parity bits in last position parity bits average inserted perm perm+spacing 35 30 25 20 15 10 5 0 mcf parser -5 gzip vpr mesa art ammp perlbmk bzip2 vortex gcc equake -10 -15 Fig. 10 22/27 NTUST ET LPS LAB
Theoretical Optimization Results vs. Realistic Values 40 35 30 25 20 15 10 5 0 k e p r x p r a 2 t f m c k m e p r p s c e c i a m a s z e t v b m r i r g m u g z a o l q b r p a v e e p Fig. 11 perm (H SP ICE ) perm (th eoretical) 23/27 NTUST ET LPS LAB
Coupling Effect Reduction for Different Partitioned Methods perm(no partition) perm+partition parity perm+partion parity and instru 40 35 30 25 20 15 10 5 0 f p x r a e r k 2 p t c p r c s k m e p e m i c a v m z e s t i a g m r r g m b z u o a b l q p r v a e e p Fig. 12 24/27 NTUST ET LPS LAB
Power Reduction of Partitioned Fault-tolerant Bus perm+spacing(no partition) perm+spacing+partition parity perm+spacing+partition parity with shield 40 35 30 25 20 15 10 5 0 e a r x c p r t f p k 2 p r c k e c s m e i a m p z m s v e a g t i g m r r u m b z a o l b q p v a r e e p Fig. 13 25/27 NTUST ET LPS LAB
Conclusion • Our fault-tolerant bus architecture using graph theory algorithm can efficient reduce coupling compared to realistic experimental result. • Nearly no additional area and timing delay • Finding a optimization solution in a polynomial-time • Partition fault-tolerant bus architecture using graph theory algorithm also can efficient save energy. • Easy to merge into nowadays’ design flow 26/27 NTUST ET LPS LAB
Thanks for Your Attention! 27/27 NTUST ET LPS LAB
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