Multi-Core Model Checking Alfons Laarman November 14, 2013 ... - PowerPoint PPT Presentation

UNIVERSITY OF TWENTE. Formal Methods & Tools. Multi-Core Model Checking Alfons Laarman November 14, 2013

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... State Space Explosion An exponential problem ◮ system data ◮ system components ◮ property size (LaQuSo project) UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 2 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... State Space Explosion An exponential problem ◮ system data ◮ system components ◮ property size (LaQuSo project) Approach ◮ multi-core model checking UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 2 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... State Space Explosion An exponential problem ◮ system data ◮ system components ◮ property size (LaQuSo project) Approach ◮ multi-core model checking ◮ Confluence / partial-order reduction ◮ Symbolic techniques (BDD-based and SAT-based) ◮ On-the-fly techniques ◮ Compression techniques UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 2 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Multi-Core Model Checking Research questions ◮ Can model checking scale (linearly, ideally) on modern multi-cores? 50 dfsfifo Speedup: ● garp ● giop2.nomig 40 i−protocol2 S P = T seq / T P leader5 ● ● 30 Speedup Ideal: S P = P ● 20 Linear: ● 10 S P = P / c ● ● 0 0 10 20 30 40 50 Threads UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 3 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Multi-Core Model Checking Research questions ◮ Can model checking scale (linearly, ideally) on modern multi-cores? ◮ Formalisms: plain, timed, stochastic, etc ◮ Properties: Reachability, LTL, CTL, etc 50 dfsfifo Speedup: ● garp ● giop2.nomig 40 i−protocol2 S P = T seq / T P leader5 ● ● 30 Speedup Ideal: S P = P ● 20 Linear: ● 10 S P = P / c ● ● 0 0 10 20 30 40 50 Threads UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 3 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Multi-Core Model Checking Research questions ◮ Can model checking scale (linearly, ideally) on modern multi-cores? ◮ Formalisms: plain, timed, stochastic, etc ◮ Properties: Reachability, LTL, CTL, etc ◮ Are our parallel solutions compatible with other techniques? 50 dfsfifo Speedup: ● garp ◮ Partial-order reduction (POR) ● giop2.nomig 40 i−protocol2 S P = T seq / T P leader5 ● ◮ Symbolic exploration ● 30 Speedup + Ideal: S P = P ● ◮ On-the-fly techniques 20 Linear: ● ◮ Compression techniques 10 S P = P / c ● ● 0 0 10 20 30 40 50 Threads UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 3 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Challenges Di ffi culties of parallelism ◮ Correctness of data structures and algorithms UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 4 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Challenges Di ffi culties of parallelism ◮ Correctness of data structures and algorithms ◮ Steep memory hierarchies UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 4 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Challenges Di ffi culties of parallelism ◮ Correctness of data structures and algorithms ◮ Steep memory hierarchies ◮ Cache coherence protocol #define B (1024 � 1024 � 1024) int main ( void ) { int result = 0; for ( int i = 0; i < B; i++) result++; return result; } UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 4 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Challenges Di ffi culties of parallelism ◮ Correctness of data structures and algorithms ◮ Steep memory hierarchies ◮ Cache coherence protocol #define P 16 static void count ( void � arg) { int � counter = ( int � ) arg; for ( int i = 0; i < B / P; i++) ( � counter)++; } int main ( void ) { pthread t thread[P]; int counters[P] = 0; for ( int i = 0; i < P; i++) #define B (1024 � 1024 � 1024) pthread create (&thread[i], NULL, count, &counters[i]); int main ( void ) { int result = 0; int result = 0; for ( int i = 0; i < P; i++) { for ( int i = 0; i < B; i++) pthread join (thread[i], NULL); result++; result += counters[i]; return result; } } return result; } UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 4 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Challenges Di ffi culties of parallelism ◮ Correctness of data structures and algorithms ◮ Steep memory hierarchies ◮ Cache coherence protocol #define P 16 T 16 = 32 static void count ( void � arg) { int � counter = ( int � ) arg; for ( int i = 0; i < B / P; i++) ( � counter)++; } int main ( void ) { pthread t thread[P]; int counters[P] = 0; for ( int i = 0; i < P; i++) #define B (1024 � 1024 � 1024) T = 27 pthread create (&thread[i], NULL, count, &counters[i]); int main ( void ) { int result = 0; int result = 0; for ( int i = 0; i < P; i++) { for ( int i = 0; i < B; i++) pthread join (thread[i], NULL); result++; result += counters[i]; return result; } } return result; } UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 4 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Challenges Di ffi culties of parallelism ◮ Correctness of data structures and algorithms ◮ Steep memory hierarchies ◮ Cache coherence protocol (false sharing) #define P 16 T 16 = 32 static void count ( void � arg) { T 16 = 1 . 8 int � counter = ( int � ) arg; for ( int i = 0; i < B / P; i++) ( � counter)++; } int main ( void ) { pthread t thread[P]; int attribute ((aligned(64))) counters[P] = 0; for ( int i = 0; i < P; i++) #define B (1024 � 1024 � 1024) T = 27 pthread create (&thread[i], NULL, count, &counters[i]); int main ( void ) { int result = 0; int result = 0; for ( int i = 0; i < P; i++) { for ( int i = 0; i < B; i++) pthread join (thread[i], NULL); result++; result += counters[i]; return result; } } return result; } UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 4 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... (Explicit-state) reachability Problem: find all reachable states from s 0 ∈ S using a next-state function: post ( S ) → 2 S A state s ∈ S is a (fixed) K -sized vector: � v 1 ,..., v K � UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 5 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Static partitioning or shared hash table store store Worker 1 Worker 2 Queue Queue Queue Queue Worker 3 Worker 4 store store UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 6 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Static partitioning or shared hash table store store Worker 1 Worker 2 Queue Queue Queue Queue Worker 3 Worker 4 store store Static partitioning X On-the-fly (BFS) ± Scalability (communication on queues) UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 6 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Static partitioning or shared hash table store store Queue Queue Worker 1 Worker 2 Worker 1 Worker 2 Queue Queue Store Queue Queue Worker 4 Worker 3 Worker 3 Worker 4 Queue Queue store store Load balancer Static partitioning Shared hash table X On-the-fly (BFS) ✓ On-the-fly: (pseudo) DFS & BFS ± Scalability (communication on queues) ? Scalability UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 6 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Lockless Hash Table: Design Laarman, van de Pol, Weber [fmcad10] Main bottlenecks ◮ State store: concurrent access ◮ Graph traversal: Random memory access (bandwidth) UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 7 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Lockless Hash Table: Design Laarman, van de Pol, Weber [fmcad10] Main bottlenecks ◮ State store: concurrent access ◮ Graph traversal: Random memory access (bandwidth) |state| |cache line| Design ◮ Hash memoization ◮ Walking the Line ◮ In-situ locking bucket data UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 7 / 27

... Introduction Reachability LTL Timed Automata LTSmin Conclusions ... Experiments from 2010 (BEEM database) SPIN 5.2.4 (NASA/JPL) DiVinE 2.2 (Brno,CZ) LTSmin (shared hash table) UNIVERSITY OF TWENTE. Multi-Core Model Checking November 14, 2013 8 / 27