METAMOC: Modular Execution Time Analysis Using Model Checking Mads - PowerPoint PPT Presentation

METAMOC: Modular Execution Time Analysis Using Model Checking Mads Chr. Olesen < mchro@cs.aau.dk > joint work with Andreas Engelbredt Dalsgaard, Martin Toft, Ren´ e Rydhof Hansen, Kim Guldstrand Larsen Aalborg University July 6th 2010

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Overview of METAMOC 1/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Overview of METAMOC Annotated Pipeline Main memory Cache executable (UPPAAL model) (UPPAAL model) specifications disassemble generate generate (objdump, Dissy) (cache−gen) (Assembly−to−UPPAAL) Control Flow Graph Caches Assembly combine (UPPAAL model) (UPPAAL models) value analysis Complete model model check (WALi) (UPPAAL model) (UPPAAL) WCET 2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Overview of METAMOC Annotated Pipeline Main memory Cache executable (UPPAAL model) (UPPAAL model) specifications disassemble generate generate (objdump, Dissy) (cache−gen) (Assembly−to−UPPAAL) Control Flow Graph Caches Assembly combine (UPPAAL model) (UPPAAL models) value analysis Complete model model check (WALi) (UPPAAL model) (UPPAAL) WCET 2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Overview of METAMOC Annotated Pipeline Main memory Cache executable (UPPAAL model) (UPPAAL model) specifications disassemble generate generate (objdump, Dissy) (cache−gen) (Assembly−to−UPPAAL) Control Flow Graph Caches Assembly combine (UPPAAL model) (UPPAAL models) value analysis Complete model model check (WALi) (UPPAAL model) (UPPAAL) WCET 2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Overview of METAMOC Annotated Pipeline Main memory Cache executable (UPPAAL model) (UPPAAL model) specifications disassemble generate generate (objdump, Dissy) (cache−gen) (Assembly−to−UPPAAL) Control Flow Graph Caches Assembly combine (UPPAAL model) (UPPAAL models) value analysis Complete model model check (WALi) (UPPAAL model) (UPPAAL) WCET 2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Overview of METAMOC Annotated Pipeline Main memory Cache executable (UPPAAL model) (UPPAAL model) specifications disassemble generate generate (objdump, Dissy) (cache−gen) (Assembly−to−UPPAAL) Control Flow Graph Caches Assembly combine (UPPAAL model) (UPPAAL models) value analysis Complete model model check (WALi) (UPPAAL model) (UPPAAL) WCET 2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Overview of METAMOC Annotated Pipeline Main memory Cache executable (UPPAAL model) (UPPAAL model) specifications disassemble generate generate (objdump, Dissy) (cache−gen) (Assembly−to−UPPAAL) Control Flow Graph Caches Assembly combine (UPPAAL model) (UPPAAL models) value analysis Complete model model check (WALi) (UPPAAL model) (UPPAAL) WCET 2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Overview of METAMOC Annotated Pipeline Main memory Cache executable (UPPAAL model) (UPPAAL model) specifications disassemble generate generate (objdump, Dissy) (cache−gen) (Assembly−to−UPPAAL) Control Flow Graph Caches Assembly combine (UPPAAL model) (UPPAAL models) value analysis Complete model model check (WALi) (UPPAAL model) (UPPAAL) WCET 2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Overview of METAMOC Annotated Pipeline Main memory Cache executable (UPPAAL model) (UPPAAL model) specifications disassemble generate generate (objdump, Dissy) (cache−gen) (Assembly−to−UPPAAL) Control Flow Graph Caches Assembly combine (UPPAAL model) (UPPAAL models) value analysis Complete model model check (WALi) (UPPAAL model) (UPPAAL) WCET 2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Overview of METAMOC Annotated Pipeline Main memory Cache executable (UPPAAL model) (UPPAAL model) specifications disassemble generate generate (objdump, Dissy) (cache−gen) (Assembly−to−UPPAAL) Control Flow Graph Caches Assembly combine (UPPAAL model) (UPPAAL models) value analysis Complete model model check (WALi) (UPPAAL model) (UPPAAL) WCET 2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Overview of METAMOC Annotated Pipeline Main memory Cache executable (UPPAAL model) (UPPAAL model) specifications disassemble generate generate (objdump, Dissy) (cache−gen) (Assembly−to−UPPAAL) Control Flow Graph Caches Assembly combine (UPPAAL model) (UPPAAL models) value analysis Complete model model check (WALi) (UPPAAL model) (UPPAAL) WCET 2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Overview of METAMOC Annotated Pipeline Main memory Cache executable (UPPAAL model) (UPPAAL model) specifications disassemble generate generate (objdump, Dissy) (cache−gen) (Assembly−to−UPPAAL) Control Flow Graph Caches Assembly combine (UPPAAL model) (UPPAAL models) value analysis Complete model model check (WALi) (UPPAAL model) (UPPAAL) WCET 2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Overview of METAMOC Annotated Pipeline Main memory Cache executable (UPPAAL model) (UPPAAL model) specifications disassemble generate generate (objdump, Dissy) (cache−gen) (Assembly−to−UPPAAL) Control Flow Graph Caches Assembly combine (UPPAAL model) (UPPAAL models) value analysis Complete model model check (WALi) (UPPAAL model) (UPPAAL) WCET 2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Current Work Support for pipelines ARM9TDMI ARM7TDMI ATMEL AVR 8-BIT Support for instruction/data caches Automatically generated LRU/FIFO replacement policy Value analysis for predicting memory accesses Implemented using Weighted Push-Down Systems Inter-procedural Currently syntactic constant-propagation Timing anomalies cannot be (consistently) handled Experiments with caches are with LRU caches, not FIFO as on the real ARM9 3/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Modelling in METAMOC Main memory TA Caches Instruction cache TA Data cache TA Pipeline Decode stage TA Memory stage TA Fetch stage TA Execute stage TA Writeback stage TA Synchronisation Process function TAs Dependency through code Overview of the ARM9 automata 4/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Modelling in METAMOC main foo fetch! fooCall? fooReturn! fooCall! fetch! done! fooReturn? Sketch of the function automata for a process 5/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Modelling in METAMOC ARM920T ARM9TDMI pipeline Caches Fetch stage Instruction cache Decode stage Memory stage Data cache Execute stage Writeback stage Main memory Fetch Decode Execute Memory Writeback fetch? decode? execute? memory? writeback? w m d e x r e e i e t c m e o c u o b d a t r e e y c ! k ! ! ! done? f_done? d_done? e_done? m_done? f_done! d_done! e_done! m_done! ARM9 overview and sketch of pipeline automata 6/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work UPPAAL 7/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work UPPAAL 8/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work UPPAAL 9/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work UPPAAL Zones 10/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work UPPAAL Zones Delay is cheap - large zones Resilient to different memory wait delays Many small steps expensive - smaller zones Zones can be collapsed, overapproximation 11/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Eliminating non-determinism Since no timing anomalies, cut down on the number of distinct paths as much as possible Pigeonhole optimisations Iterate loops the maximum number of times Don’t forward jump if path is subset of not jumping “Executing more code increases the execution time” Can be disabled if timing anomalies present 12/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Experiments Evaluation using WCET benchmark programs from M¨ alardalen Real-Time Research Centre Applicability Performance Discarded a number of programs Floating point operations handled by software routines Dynamic jumps Some programs do not compile for our architectures 21 programs for ARM and 19 programs for AVR Manually annotated loop bounds 13/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work Experiments Relative improvement in WCET for Analysis times in minutes for AVR ARM9. and ARM9. 14/17