LRR-DPUF: Learning Resilient and Reliable Digital Physical - PowerPoint PPT Presentation

LRR-DPUF: Learning Resilient and Reliable Digital Physical Unclonable Function Jin Miao 1 Meng Li 2 Subhendu Roy 1 Bei Yu 3 1 Cadence Design Systems 2 University of Texas at Austin 3 The Chinese University of Hong Kong 1 / 26

Outline Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion 2 / 26

Outline Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion 3 / 26

Introduction Conventional analog silicon PUFs ◮ Transistor analog intrinsic randomness ◮ Vulnerable to environmental and operational variations ◮ Need error correction Expected digital silicon PUF ◮ Boolean type randomness source ◮ Immune to environmental and operational variations ◮ Less to no error correction ◮ Strong resilience to attacks 4 / 26

Introduction Related work ◮ Hybrid FPGA digital PUF however need analog PUF to start up [FPL ’14] ◮ First digital PUF by interconnection uncertainty yet only conceptual and less feasible for practice [ISQED’15] Contributions in our work ◮ Quantitative justifications of the use of interconnect randomness ◮ Strongly skewed latches to ensure deterministic transistor behaviors ◮ Novel highly non-linear logic network to ensure strong security 5 / 26

Outline Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion 6 / 26

Lithography variations Identify a feasible source of Boolean randomness is half the battle to make a digital PUF. Two slightly differed mask stripe-pairs are eventually mapped to have different connectivities on silicon. 3nm 5nm Interconnect under lithography variation. Left: mask split of 20 nm for top, 28 nm for bottom. Right: shapes on wafer. 7 / 26

Lithography variations Lithography variation categories ◮ Systematic : dose, focus, etc. ◮ Local : mask, line edge roughness (LER), etc. Mask error for interconnect randomness ◮ Position two interconnect layout line-ends close to each other ◮ An electron beam system can easily lead to large mask variations ◮ Mask variation further maps to different connectivity in wafer 8 / 26

Lithography variations Quantitative justifications of lithography variations ◮ The existence and control of the configurations to ◮ Augment the local variation ◮ Suppress the systematic variation 1.05 1 1 0.95 1 Connectivity Rate 0.9 Connectivity Rate Connectivity Rate 0.9 0.95 0.8 selected mean 0.85 0.9 0.7 0.8 0.85 0.6 0.75 0.8 selected stdv. 0.5 0.7 0.75 0.65 0.4 0.7 0.6 35 40 45 50 0 1 2 3 4 5 0.98 0.99 1 1.01 1.02 Layout Split Distance (nm) Mask Error Stdv. Distance (nm) Dose Value (normalized) Interconnect connectivity rate under lithography variations: Left: layout split distance under mask error stdv. of 4 nm ; Center: mask error stdv. under split of 46 nm ; Right: dose values. Conclusion Lithography variations can be utilized by careful configurations of layout split and E-beam accuracy. 9 / 26

Outline Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion 10 / 26

Unit Cell Naïve random interconnection is incompatible to digital CMOS. ◮ Short-circuit : direct current from Vdd to Gnd, uncertain region, etc. ◮ Open-circuit : floating gate, etc. Goal: Pure logical circuit compatible for normal and open circuits Strongly skewed latch! 1 A skew-1 B skewed-1 inv skewed-0 inv 0.8 0.6 V B (V) 0.4 skew-0 0.2 0 0 0.2 0.4 0.6 0.8 1 V A (V) Handling dangled poly-gate by strongly skewed latch. Left: inverter pair based skewed latch; Right: the VTC relation of a strongly skewed latch. 11 / 26

Unit Cell Exclusive-OR (XOR) cell property ◮ Linear non-separable response is 0 response is 1 A A 1 1 1 0 0 B 1 1 B C (a) (b) Linear non-separable nature for XOR logic. ◮ Equal output probability If Pr [ a = 1 ] = Pr [ a = 0 ] = 0 . 5 , ∀ b ∈ B , then Pr [ y = 1 ] = Pr [ y = 0 ] = 0 . 5 . 12 / 26

Unit Cell The proposed unit cell virtual connection virtual connection skew-0 skew-1 key output output key Left: the complete unit cell logic structure; Right: simplified symbolic representation. A unit cell may or may not invert its key depending on virtual connection . 13 / 26

Outline Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion 14 / 26

LRR-DPUF architecture The proposed LRR-DPUF architecture Z Z Z … … in0 out0 … … in1 out1 … … in2 out2 N rows … … in3 out3 … … in4 out4 … … … … … … … … … … … … … … inN-1 … … outN-1 Z Z Z M colums A N-row by M-col LRR-DPUF architecture. Some boundary virtual connections are marked by “ Z ” indicating dangling status. Each row is a signal tunnel where the 1-bit input signal may be inverted depending on the virtual connections associated to this row. 15 / 26

LRR-DPUF architecture LRR-DPUF formula k i , j − 1 ⊕ ( v · k i + 1 , j − 1 + v ) , i even, j even;    k i , j − 1 ⊕ ( v · k i − 1 , j − 1 + v ) ,  i even, j odd;  k i , j = k i , j − 1 ⊕ ( v · k i − 1 , j + v ) , i odd, j even;     k i , j − 1 ⊕ ( v · k i + 1 , j + v ) , i odd, j odd. Here k i , j refers to i - row j - column output, and v refers to virtual connection status. 16 / 26

LRR-DPUF architecture Logic cone of an 8 × 8 LRR-DPUF Z Z Z Z in0 out0 in1 out1 in2 out2 in3 out3 in4 out4 in5 out5 in6 out6 in7 out7 Z Z Z Z Logic cone of out 2 is highlighted in red color. 17 / 26

LRR-DPUF architecture LRR-DPUF properties ◮ The non-linearity of LRR-DPUF increases along with a higher connectivity rate. ◮ There is a sufficiently large space of unique LRR-DPUFs even if the connectivity rate is high. ◮ Increasing the number of columns strengthens the resilience to learning attacks. ◮ Any subtle change on virtual connections will be reflected to multiple outputs. 18 / 26

Outline Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion 19 / 26

Evaluation Statistical evaluation Table: Statistical evaluation on 8 × 8 LRR-DPUF with 256 exhaustive CRPs conn. rate = 0.2 conn. rate = 0.9 Type (Ideal Value) Mean Stdv. Mean Stdv. Inter HD (0.5) 0.4188 0.0302 0.4943 0.0061 Intra HD (0.0) 0 0 0 0 Bit Alias (0.5) 0.5000 0.2067 0.5000 0.0730 Uniformity (0.5) 0.5000 0.1768 0.5000 0.1678 Table: Statistical evaluation on 64 × 64 LRR-DPUF with 100K CRPs conn. rate = 0.2 conn. rate = 0.9 Type (Ideal Value) Mean Stdv. Mean Stdv. Inter HD (0.5) 0.4999 0.0009 0.5000 0.0009 Intra HD (0.0) 0 0 0 0 Bit Alias (0.5) 0.5000 0.0504 0.5000 0.0499 Uniformity (0.5) 0.5000 0.0625 0.5000 0.0624 20 / 26

Evaluation Avalanche effect 8 con. ratio = 0.9 7 con. ratio = 0.2 Impacted Output # 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 i th Input Bit Avalanche effect of 8 × 8 LRR-DPUF over each input. Under high connectivity rate, the adversary prediction via one bit change at a time is no better than a simple random guess. 21 / 26

Evaluation Adversary attacks: 8-row by various number of columns 55% 60% 8-row, 128-col 8-row, 128-col 50% 55% 8-row, 32-col 8-row, 32-col 8-row, 16-col 8-row, 16-col 45% 50% 8-row, 8-col 8-row, 8-col Prediction Error Prediction Error 40% 45% 35% 40% 30% 35% 25% 30% 20% 25% 15% 10% 20% 0% 20% 40% 60% 80% 100% 0% 20% 40% 60% 80% 100% Training Set Ratio Training Set Ratio SVM attack for 8-row LRR-DPUFs over different configurations: Left: connectivity rate of 0.2 over different column sizes and training sizes; Right: connectivity rate of 0.9 over different column sizes and training sizes; 22 / 26

Evaluation Adversary attacks: 64-row by 64-colum 80% RF w/ con. ratio = 90% con. ratio = 90% 54% RF w/ con. ratio = 20% 70% con. ratio = 20% ANN w/ con. ratio = 90% con. ratio = 10% 60% ANN w/ con. ratio = 20% Prediction Error Prediction Error con. ratio = 1% 52% 50% 50% 40% 30% 48% 20% 10% 46% 0% 0% 20% 40% 60% 80% 100% 0% 20% 40% 60% 80% 100% Training Set Ratio Training Set Ratio Left: SVM attacks over different connectivity rate and training size. Right: additional learning model attacks including i) Artificial neural network (ANN) with 10 hidden layers using Sigmoid function, and ii) Random Forest (RF) with 15 trees in the forest. 23 / 26

Outline Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion 24 / 26

Conclusion ◮ A novel learning resilient and reliable digital PUF ◮ Justification for the use of interconnect randomness ◮ Strongly skewed latches for CMOS compatibility ◮ A highly non-linear logic architecture 25 / 26

Thank You Jin Miao (jmiao@cadence.com) Meng Li (meng_li@utexas.edu) Subhendu Roy (subhroy@cadence.com) Bei Yu (byu@cse.cuhk.edu.hk) 26 / 26