2-3.1 2-3.2 Learning Outcomes • I understand the active-low signal convention and how to interface circuits that use both active-high and active-low signals Spiral 2-3 • I can take any state diagram and create a corresponding state machine using one-hot implementation by using one FF per state and creating the D-input circuit by converting each Negative Logic incoming transition arrow to a state into a logic gate and OR- ing them together One-hot State Assignment System Design Examples • I understand how to decompose an algorithm into states for each step and appropriate datapath units for each operator 2-3.3 2-3.4 DeMorgan Equivalents = = = NEGATIVE (ACTIVE-LO) LOGIC =
2-3.5 2-3.6 Negative Logic Why Active-low • Recall it is up to us humans to _______________ to the two voltage levels • Some digital circuits are better at _________ – Thus, far we’ve used (unknowingly) the ___________ logic convention where (draining/sucking) electric current than 1 means true and 0 means false – In _____________ logic 0 means true and 1 means false _____________ (producing) current 1=true/on 1=false/off volts volts (Value/Meaning) (Value/Meaning) Active-hi output Active-low output 0=false/off 0=true/on LED is on when LED is on when time time gate outputs '1' gate outputs '0' ___________ Logic ___________ Logic Convention Convention 2-3.7 2-3.8 Negative Logic ‘AND’ Function Negative Logic ‘OR’ Function Traditional N.L. AND N.L. AND = Traditional N.L. OR N.L. OR = P.L. AND function P.L. OR P.L. OR function P.L. AND N.L. N.L. P.L. P.L. N .L. N .L. N.L. N.L. X X P.L. P.L. X X N .L. P.L. P.L. Z P.L. Z Z X Z AN D P.L. OR AND AND Y Z Y Y Y OR Y N.L. OR N.L. AND X Y Z X Y Z X Y Z X Y Z X Y Z X Y Z 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 1 1 0 1 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 Traditional AND gate Given negative logic However, we then see that Traditional OR gate Given negative logic However, we then see that functionality assumes signals, we can invert to an OR gate implements the functionality assumes signals, we can invert to an AND gate implements positive logic positive logic, perform the negative logic ‘AND’ positive logic positive logic, perform the the negative logic ‘OR’ convention AND operation, then function convention OR operation, then convert function convert back to negative back to negative logic logic
2-3.9 2-3.10 Negative Logic Active-hi vs. Active-low • Active-hi convention – 1 = on/true/active A negative logic OR function is equivalent to an AND gate – 0 = off/false/inactive = • Active-low convention – 0 = on/true/active A negative logic AND function is equivalent to an OR gate – 1 = off/false/inactive = • To convert between conventions – ___________________ These are the preferred way of showing the N.L. functions because the inversion bubbles explicitly show where N.L. is being converted to P.L. and the basic gate schematics retain their meaning (when we see an AND gate we know we’re doing some king of AND function with the bubbles indicating N.L.) 2-3.11 2-3.12 Enables Decoder w/ Active Low Enable and Outputs 0 1 0 When E=0, Since E=0, inputs is all outputs = 0 0 0 ignored 0 /D0 A 0 /D1 /D2 B /D3 0 When E=1, /E 1 1 inputs will cause the Since E=1, appropriate output to 0 outputs will Bubbles and signals starting with a 0 Enable go active function normally 0 slash '/' indicate an active-low input or output…not an inverter…the 1 inverters are actually in the logic diagram on the next pages…
2-3.13 2-3.14 Active-Lo Outputs Active-Lo Enable When E=inactive (inactive means 0), Outputs turn off (off means 1) When E=inactive (inactive means 1), Outputs turn off (off means 0) When E=active (active means 1), Selected outputs turn on (on means 0) When E=active (active means 0), Selected outputs turn on (on means 1) 2-3.15 2-3.16 Active-Lo Enable Decoder w/ Multiple Enables • When a decoder has multiple enables, all enables ________________ for the decoder to be enabled 3 Enables /G1 must equal 0 /G2 must equal 0 When E=inactive (inactive means 1), Outputs turn off (off means 1) and E must equal 1 When E=active (active means 0), Selected outputs turn on (on means 0)
2-3.17 2-3.18 Active Low CLR and PRESET Active Low CLR and PRESET • The reset signal might also be active low • Need to be able to initialize Q to a known value (0 or (0 = Reset, 1 = Normal operations) 1) • FFs can be made with active low /CLR & /PRE /RESET /RESET 1 1 PRE PRE When /RESET = 0, When /RESET = 1, Logic _ Logic Q* = _ D Q D Q /CLR is activated /CLR is inactive and and Q is forced to 0 Q looks at D at each CLK CLK clock edge CLR CLR /RESET /RESET _ _ 2-3.19 2-3.20 Digital System Representation Turn Sensor S1 State Diagram Overall sensor Turn Sensor output S2 S = S1 + S2 Main Street Conditioned FF FF Raw inputs ONE-HOT STATE ASSIGNMENT inputs inputs outputs S1 S Outputs S2 Input Function Logic Next State State Output Function (IFL) Logic Memory Logic (NSL) (SM) (OFL)
2-3.21 2-3.22 Encoded State Assignment Review State Assignment State Diagrams State Machine • Design of the traffic light controller with main turn arrow 1. States 1. State Memory => FF’s • Represent states with some binary code, but what kind? – n-FF’s => 2 n states 2. Transition Conditions 2. Next State Logic (NSL) + – Encoded: 3 States => __________ : ___=SSG, ___=MSG, ___=MTG 3. Outputs Input Function Logic (IFL) – One-hot: Separate FF per state: ___=SSG, ____=MSG, ____=MTG – combinational logic for FF inputs Turn 3. Output Function Logic (OFL) Sensor S1 – MOORE: f(state) State Machines require sequential logic to remember the current state – MEALY: f(state + inputs) (w/ just combo logic we could only look at the current value of X, but now we can take 4 separate (Input) (Next State) (Current State) actions when X=0) State X D 0 Q 0 OFL D Q Diagram X=1 On Reset (Output) (power on) NSL X=1 X=0 X=1 Q F S101 Sinit S1 S10 SM Overall sensor F=0 F=0 F=0 F=1 D 1 Q 1 Turn X=0 X=1 D Q Sensor output S2 S = S1 + S2 X=0 Q X=0 State Diagram for “101” Main Street Sequence Detector CLK 2-3.23 2-3.24 NSL Implementation in 1-Hot Method NSL Implementation in 1-Hot Method • In one-hot assignment, NSL is Q SS Q MT Q MS • Two arrows converge on MS: Q SS Q MT Q MS designed by simple observation “Q MS should be ‘1’ on the next SS 1 0 0 SS 1 0 0 • For each state, examine each clock when… MT 0 1 0 MT 0 1 0 ____________ transition – Current state is MT ...OR… MS 0 0 1 MS 0 0 1 – Each incoming arrow will be one case in – Current stat is SS AND S=0 our logic One-hot State Assignment One-hot State Assignment • Q* MS = D MS = Q MT + Q SS • • S’ • • – We can just ____ each condition together • Describe each transition as a combination of what state it • Q* MT = D MT = originates from & any associated conditions • Q* SS = D SS = • Ex. Two arrows converge on MS: “Q MS should be ‘1’ on the next clock when… • What about initial state? Preset – Current state is _____ ...OR… the appropriate flop. – Current state is ____ AND _____
2-3.25 2-3.26 Multiplication Techniques • A multiplier unit can be – Purely Combinational: Each partial product is produced in ____________ and fed into an _______ of adders to generate the product – Sequential and Combinational: Produce and add 1 Array Multiplier (Combinational) partial product at a time (_______________) Add and Shift Method (Sequential) MULTIPLICATION TECHNIQUES 2-3.27 2-3.28 Add and Shift Method Combinational Multiplier Analysis • Sequential algorithm • Large Area due to ____________-bit adders • n-bit * n-bit multiply – n-1 because the first adder adds the first two • Adds 1 partial product per clock partial products and then each adder afterwards • Shift running sum 1-bit right each clock adds one more partial product • Three n -bit Registers, 1 Adder • Propagation delay is in two dimensions • At start: – proportional to ________ – M = Multiplicand – Q = Multiplier – A = Answer => initialized to 0 • After completion – A and Q concatenate to form 2 n -bit answer
2-3.29 2-3.30 Add and Shift Hardware Add and Shift Algorithm 1010 = M • C=___, A=____ * 1011 = Q • Repeat the following _____________ C A Q – If Q[0] = 0, A = _______ 1 0 1 1 0 0 0 0 0 Else if Q[0] = 1, A= ______ – Shift _____ 1-bit (0→___________) Cout 0 Cin 0 1010 M 2-3.31 2-3.32 Add and Shift Multiplication 1010 = M * 1011 = Q 01101110 = Ans 1010 C A Q * 1011 0 0 0 0 0 1 0 1 1 M = 1010 C A Q Cout 0 0000 1011 0 Cin 0 1010 M
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