IROC Technologies General Presentation June 2014
Who is IROC Technologies? History: Established in 2000 in France as a spin-off from a R&D lab US Corp launched in 2001 Memory BIST product & team acquired by Synopsys in 2004 Activity: Solutions for analyzing and improving the overall reliability of devices Focus on Single Event Effects Moving on process variability, environment stress, ageing Leading commercial provider of soft error solutions: More than 200 soft error test campaigns Serving major players in many segment of the industry (foundries, fabless, IDM, system houses) Solutions roadmap in line with market needs Established network of well recognized collaborators: nuclear database, neutron labs, alpha counting equipment suppliers 2
SEEs – Why Should I Care Usual fields: Aero-space applications A satellite was launched from Baikonor Cosmodrome, Kazakhstan on 31 May 2005 Failed during the 5th orbit instead of after a total of 253 orbits (2% use) Failure Site -> Source: Reno Harboe-Sørensen, ESA- ESTEC, ” Radiation Effects in Spacecraft Electronics“, 5th LHC Radiation Workshop – Nov-29, 2005. A latch-up condition in a SRAM was concluded as the possible cause SEEs: Coming down to Earth 1970’s: First studies on SRAM susceptibility to alpha particles… and still many years later: 2000’s: Alpha problems in CPU cache memories (used in high-reliability servers) Elections in Belgium: electronic voting machines on 05/18/2003 (Schaerbeek): More votes compared to number of registered persons: shift of … 4096 votes ! A SEU effect on 13th bit in SRAM was considered as the possible causes Now: Atmospheric neutrons, low energy protons, multi-cell errors, transients, X-rays dose effects in DRAMs
Backgrounder: The Soft Error/ SER Problem Electrons Bit flip, Transistor Neutrons Transient pulse Ions @ sea level e - Si 25 Mg+ α e - n 28 Al+p 24 Mg+n+ α Si e - Packaging α e - Impurities e - 7 Li+ α n th 10 B Nuclear Physics Silicon Reaction Understanding the Phenomena Requires a Combination of Nuclear Physics & Semiconductor Device Physics
SER trends in Cells wrt Process Node Even though per memory bitcell SER sensitivity is decreasing, overall FIT per SoC is increasing 700 700 FIT/Mb 600 600 SRAM SER FIT rate per node FF SEU FIT rate per node 500 500 400 400 300 300 200 200 100 100 0 0 400 300 200 100 0 200 150 100 50 0 SBU Average/node SEU Average/node MCU Average/node Expon. (SBU Average/node) Linear (SEU Average/node) Expon. (MCU Average/node) Atmospheric Neutron Results Alpha results are similar assuming an Ultra Low Alpha Emissivity Rate package
SER trends in SoC wrt Process Node 1000 FIT Typical SoC SER FIT rate per design 100 10 1 200 180 160 140 120 100 80 60 40 20 0 Node (nm) Memory SER Logic SER (Seq + Comb) Expon. (Memory SER) Expon. (Logic SER (Seq + Comb))
SEEs: A challenging aspect of System Reliability Environment SER Data System SER User SER Raw Cell SER Circuit SER Single Event Effects (SEEs) - A threat to all the reliability metrics Data Integrity Availability Maintainability Managing SER aspects – an industry-wide topic Inter-company collaboration – materials suppliers, foundries, IP & chips providers, system integrators, etc Intra-company collaboration – system architect, reliability engineer, hardware designer, software engineer
IROC Scope and Objectives Functional Failure Single Event Fault Soft Error Single Event Transient Soft Error in Logic Single Event Upset Single Event Latchup, SEGR, SEB SBU, MBU in memory Abstraction Level Increases => Sophisticated SEE Analysis Device Complexity Increases => Innovative Test Methodology Standard memories: TCAM CPUs, ASICs Boards Devices FPGAs: SRAM, DRAM, Test chips SRAM, FLASH, FLASH, etc Fuse-based, etc
IROC Offer Positioning IROC delivers test and design solutions to ensure that soft error risks are addressed and eradicated SER Product Testing TEST SERVICE Library level (characterization) Chip level (ASER/RTSER) System level (Platform Testing) Wafer alpha emission analysis Packaging Alpha emission analysis Foundry Libraries Design Packaging System DESIGN SERVICE & TOOLS Cell level Analysis Circuit Analysis Design Support Library characterization Design characterization Patented solutions for libraries FIT prediction Risk assessment Patented solutions for designs Cell optimization Intrinsic FIT prediction TFIT tool SoCFIT tool
SER Test Activities at IROC
Accelerated Neutron Shuttle Program Multiple users at the same time (stack of daughterboards) allows creating more testing opportunities for the industry.
Soft Error Testing: Accelerated Testing Sites Triumf, Vancouver TSL, Sweden Los Alamos National Labs
Neutron Shuttle Schedule • IROC tests mostly with white/atmospheric spectrum neutron labs • Alpha particles test performed at IROC. Available year round • Gamma, protons, heavy ions: pending customer need
From Components Testing… SRAM SEU, MBU, SEL, SEFI TCAM SRAM-like Analysis + Search mode SEEs DRAM Detection of memory upsets and Tref evolution FPGA Detections in configuration memory, block RAM, F/F and logic block upsets ASIC and SoC Detections in embedded memories and F/F upsets. … to Motherboard and Device Testing
Other Radiation Testing Beam Types Heavy Ions: Jyvaskyla (Finland), UCL-HIF (Belgium), IPN (France) Protons : UCL-LIF (Belgium), TSL (Sweden) Alpha: in-house capabilities; Californium : ESA ESTEC, Laser Beam: EADS (France) Applications Dedicated SET/SEU test chips: ATMEL, CNES, EADS, MindSpeed CPUs, microcontrollers: ATMEL, CNES, ESA, e2v, EADS (+Freescale) Memory devices: STM, ATMEL, others ASICs, SoCs: ATMEL, Thales, CNES Military/Aero-Space activities TID: C60 registered and calibrated source in France Displacement damage effect Prompt dose effect (X flash)
Dedicated Test-Chips for SER Measurements Process Technology characterization Transient Pulse SEU rate Width SET SEU Probe Test Speed SET Test Test Validation at SET rate high frequencies
Alpha Counting
Alpha Particles Contamination Issues The semiconductor industry has reached an extremely high level of transistor integration (65 or 45nm nodes) As a consequence, the technology is losing its natural immunization against environmental aggressions (radiations, alpha particles). Alpha particles are generated by traces of radioactive material in the packaging. They have a very high ability to generate upsets. Industry requirements call for very low to ultra low alpha emissions of materials (.01 to .001 alpha/cm 2 /hr) More and more manufacturers need to verify the emission level and the immunization of their design. IROC and Alpha Sciences, as third party independent specialists, help the industry tackle these issues
Types of Samples Measured Pellets Paste Samples (Molding compounds) (solder paste) Si wafers Solder Balls (up to 300mm) Packaged chips Powder Samples or devices
ASI Ultra Low Background Counters • Widely used in the Industry Hundreds of counters shipped, decades of experience in the field • Simple and easy to use Plug and play solution, very stable, low maintenance systems • Highly Versatile For any type of sample: solid, powder, paste, non conductive, you name it! • Very Low background on an economical system Best accuracy for the price!
Our Offering We measure any type of material or devices (as long as it fits into the counting chamber) Measurement duration takes 2 to 3 days, depending on the size of devices and alpha activity (low activity can take longer to improve the accuracy) We sell entire alpha counting system for ASI. (please contact us for price and conditions) Measurement takes place either in the US or in France, for more flexibility and convenience For more information, visit: http://www.IROCtech.com/sol_test_115.html
SER Simulation Tools
Analysis/Prediction platform Response model SER DB TFIT Analyzed SoC design SPICE NetList SoCFIT SoC RTL/Netlist
TFIT Overview A cell level soft error simulator: Input : Cell netlist, technology response model, particle type, cell layout geometry Output : SEU FIT / MCU FIT / Current pulse Limited requirement: Access to Spice Simulator tool Targeted Users: Memory Designers and Bit Cell Developers IP Development Teams (At IDM, Foundries or Fabless) Support of different radiation environments: Ions (Heavy & Alpha) Atmospheric neutrons Very fast and accurate simulator (silicon test correlated) Charge coupling and charge sharing effects included
TFIT Positioning in the Design Flow User Process Configuration SPICE Model Input response parameters netlist Card models SPICE TFIT Simulator IROC Technologies SET/SEU Output Secondary Cross section Particles SEU FIT Nuclear MCU FIT patterns Database
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