IP Authoring and Integration for HW/SW Co-Design and Reuse - - PDF document

IP Authoring and Integration for HW/SW Co-Design and Reuse - Lessons Learned Monterey, EDP 2002, Frank Schirrmeister CADENCE CONFIDENTIAL Agenda • Drivers • A Brief History in Abstraction • Tackling the Abstraction Issue – Lessons Learned – Practical Platform Based Design • Design Flows Revisited – Lessons Learned - IP Authoring – Lessons Learned - IP Integration • Conclusion – No surprises! CADENCE CONFIDENTIAL 1

Market Drivers CADENCE CONFIDENTIAL Why is Design Getting so Complicated? 2001 2002 2003 Design at this level of complexity requires moving to higher levels of abstraction Silicon Complexity 15M Gates 40M Gates 100M Gates 100M Gates 100M Gates Silicon Complexity 15M Gates 40M Gates 100M Gates 90nm Process Technology 180nm 130nm 90nm 90nm Process Technology 180nm 130nm 90nm Design in deep-submicron processes forces processing of much more detail than previously Moore’s law Moore’s law CADENCE CONFIDENTIAL 2

Why is Design Getting so Complicated? Abstraction Design at this level of complexity requires moving to higher levels Conception Conception of abstraction These two Validation Validation effects work against each other Implementation Implementation Design in deep-submicron D e t processes forces processing of a i l much more detail than previously CADENCE CONFIDENTIAL A Brief History in Abstraction CADENCE CONFIDENTIAL 3

A Brief History in Abstraction The Digital Design Entry Level Hardware Software Token Different MoCs, Ptolemy, SC2.0, C++, UML, CoCentric, SPW, VCC Transaction Verilog, VHDL, SC2.0, TestBuilder C, C++ {Verilog,VHDL} RTL, SC1.0 Signal C {Verilog,VHDL} Gate, Schematic Transistors Technology ASM Layout 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 CADENCE CONFIDENTIAL A Brief History in Abstraction The Digital Design Entry Level Hardware Software Token Different MoCs, Ptolemy, SC2.0, C++, UML, CoCentric, SPW, VCC Transaction Verilog, VHDL, SC2.0, TestBuilder C, C++ {Verilog,VHDL} RTL, SC1.0 Signal C {Verilog,VHDL} Gate, Schematic Transistors Technology ASM Layout 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 CADENCE CONFIDENTIAL 4

A Brief History in Abstraction The Digital Design Entry Level Hardware Software Token Different MoCs, Ptolemy, SC2.0, C++, UML, CoCentric, SPW, VCC RTL Transaction Verilog, VHDL, SC2.0, TestBuilder C, C++ {Verilog,VHDL} RTL, SC1.0 Signal C {Verilog,VHDL} Gate, Schematic Transistors Technology ASM Layout 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 CADENCE CONFIDENTIAL A Brief History in Abstraction The Digital Design Entry Level Ports Register File Tasks MPEG Video Decoder DMAC Timers MPEG RTOS Audio Decoder Bus/Cache Control uC I/F Driver DRAM Ctrl Graphics Engine D-Cache I-Cache Hardware On-Chip Ram Software Token Different MoCs, Ptolemy, SC2.0, C++, UML, CoCentric, SPW, VCC SW RTL RTL Clusters Models Transaction Verilog, VHDL, SC2.0, TestBuilder C, C++ {Verilog,VHDL} RTL, SC1.0 Signal C {Verilog,VHDL} Gate, Schematic Transistors Technology ASM Layout 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 CADENCE CONFIDENTIAL 5

Tackling the Abstraction Issue Trends CADENCE CONFIDENTIAL Tackling the Abstraction Issues Practical Approaches Platform Based Design Function Architecture Co-Design – Foundation Block defining the Virtual Component Co-Design 1 1 2 2 domain System System System System Behavior Behavior Architecture Architecture – Reference Design differentiating the Behavior Behavior Mapping Mapping design Simulation Simulation 3 3 – Derivative Design to accelerate Performance Performance Simulation Simulation incremental product Changes Refinement Communication Communication Refinement Refinement 4 4 Flow To Implementation Flow To Implementation MEM Hardware System Software Application HW Top-level Test Bench on RTOS CPU Space FPGA HW Verification SW Verification SW RTL HW/SW “C” Co-Verification P Prototype & Production CADENCE CONFIDENTIAL 6

Lessons Learned … Platform Type Examples “Full Application HW/SW Platform” “Processor Centric Platform” Examples: Examples: –TI OMAP – ARM Micropack –Philips nExperia, – ST100 Platform –Infineon MGold – Motorola Starcore Texas Instruments OMAP Arm Micropack ARM940T CPU ARM940T CPU ARM940T CPU Cache Cache Cache (ISS Integration) (ISS Integration) (ISS Integration) ARM Wrapper ARM Wrapper Counter 1 Counter 1 (API Support) (API Support) B B TImer TImer Counter 1 Counter 1 R R I I D D AHB AHB APB APB G G E E Interrupt Interrupt ASIC ASIC Memory Memory DMA DMA Controller Controller (CUSTOM IP) (CUSTOM IP) Controller Controller RAM ROM RAM ROM CADENCE CONFIDENTIAL Lessons Learned … Platform Type Examples “Communication Centric Platform” “Highly Programmable Platform” Examples: Examples – Palmchip –Triscend A7 – Sonics –Chameleon –Altera Excalibur –Xilinx Platform FPGA SONICs Architecture SONICs Architecture Open Core { DMA DSP CPU MPEG Protocol ™ MultiChip SiliconBackplane ™ Backplane ™ (patented) I O C MEM SiliconBackplane Xilinx Platform FPGA Agent ™ CADENCE CONFIDENTIAL 7

Lessons Learned Platform User Types / Hand Off Points “Power User” – differentiates at all levels – software and hardware – Develops additional custom hardware and software components “Platform Differentiator” – differentiates at the application level – develops processor Application Software – Uses existing libraries as hardware accelerators “Complete Package User” – expects complete solution (hardware and software) – limited additional development and differentiations CADENCE CONFIDENTIAL Lessons Learned Return on Investment Considerations How to assess ROI of new tools and methodologies? – How many man month does it save? – How many new engineers does the organization not have to hire? – How much faster will the product go out the door? Value per day? – How much better will the quality of results be? Semiconductor Platform Example – Reduce the number of project years required for a fast derivative from the platform Example Assumption – Reduction of Effort for derivative design from 30 man years to 10 man years – 15 derivative designs … result in 15x20=300 man years of cost reduction. CADENCE CONFIDENTIAL 8

Lessons Learned It really is a design chain … Development Centers Device & Equipment Manufacturers BSQUARE, Productivity Systems, Nokia, Ericsson, Sony, TI for Handspring, Acer Inc. (PSI), PacketVideo Partners Communications & Multimedia Inc, High Tech Computer Corporation, LG, Compal, GVC, Quanta Computer, ZTE, Sendo, Arima, ASUSTeK, Compal, DBTel, Quanta, Inventec, Tecom, Chi Mei, Ares, Inventec, TelePaq, FIC, Mitac-Synnex, Universal Scientific Industrial. Texas Instruments Partners Nokia, Ericsson, Sony, TI for Handspring, Acer System Houses TI OMAP Virtual Component Semiconductor (IP) Providers Houses SW IP: Symbian Application & Middleware Providers Virtual Component Microsoft, Real Networks, SDK & OS Consumer PacketVideo, GeoVector, TI Security (IP) Providers (EPOC), MS Lib., Atelier Phone SW, GPRS SW, WinCE, DSP AM ROAD Electronics, Ultima BIOS, OSE Electronics, ProSense, Chanceux HW IP ARM CADENCE CONFIDENTIAL Design Flows Revisited CADENCE CONFIDENTIAL 9

Traditional Integration Approaches Evaluation Before Implementation? Where and how? Hardware Software Token Different MoCs, Ptolemy, SC2.0, C++, UML, CoCentric, SPW, VCC IP Transaction Verilog, VHDL, SC2.0, TestBuilder C, C++ Authoring IP {Verilog,VHDL} RTL, SC1.0 Integration Signal C {Verilog,VHDL} Gate, Schematic Transistors Technology ASM Layout 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 CADENCE CONFIDENTIAL Traditional Integration Approaches Evaluation Before Implementation? Where and how? How to design a system block? Embedded System Requirements – Starting from the system level IP Block Definition – With a consistent test-bench – Getting from the abstract, un-timed Executable System Level system model to the clocked HW or Block Level Specification SW implementation model Example • Rake Receiver Iterative Refinement – Which are the optimal algorithms? – How does it work fixed point? Block Implementation – How is it best implemented? Implementation Level Verification – Does the implementation work as specified in the system level Synthesis / Place & Route etc. CADENCE CONFIDENTIAL 10